Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
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3.9.1. PCI Express and PCI Capabilities

Table 16.  Capabilities Registers

Parameter

Possible Values

Default Value

Description

Maximum payload size

128 bytes

256 bytes

512 bytes

1024 bytes

2048 bytes

128 bytes

Specifies the maximum payload size supported. This parameter sets the read-only value of the max payload size supported field of the Device Capabilities register (0x084[2:0]). Address: 0x084.
Note: The SR-IOV bridge supports a single value for the Maximum payload size parameter. When the configuration includes 2 or more PFs, you must program all 4 PFs for the SR-IOV bridge to specify a value larger than 128 bytes.

Number of Tags supported

32

64

32

Indicates the number of tags supported for non-posted requests transmitted by the Application Layer. This parameter sets the values in the Device Control register (0x088) of the PCI Express capability structure described in Table 9–9 on page 9–5.

The Transaction Layer tracks all outstanding completions for non‑posted requests made by the Application Layer. This parameter configures the Transaction Layer for the maximum number of Tags supported to track. The Application Layer must set the tag values in all non‑posted PCI Express headers to be less than this value. Values greater than 32 also set the extended tag field supported bit in the Configuration Space Device Capabilities register. The Application Layer can only use tag numbers greater than 31 if configuration software sets the Extended Tag Field Enable bit of the Device Control register.
Note: When more than one physical functions are enabled in the IP core, the non-posted tag pool is shared across all of them.

Completion timeout range

ABCD

BCD

ABC

AB

B

A

None

ABCD

Indicates device function support for the optional completion timeout programmability mechanism. This mechanism allows system software to modify the completion timeout value. This field is applicable only to Root Ports and Endpoints that issue requests on their own behalf. Completion timeouts are specified and enabled in the Device Control 2 register (0x0A8) of the PCI Express Capability Structure Version. For all other functions this field is reserved and must be hardwired to 0x0000b. Four time value ranges are defined:

  • Range A: 50 us to 10 ms
  • Range B: 10 ms to 250 ms
  • Range C: 250 ms to 4 s
  • Range D: 4 s to 64 s

Bits are set to show timeout value ranges supported. The function must implement a timeout value in the range 50 s to 50 ms. The following values specify the range:

  • None—Completion timeout programming is not supported
  • 0001 Range A
  • 0010 Range B
  • 0011 Ranges A and B
  • 0110 Ranges B and C
  • 0111 Ranges A, B, and C
  • 1110 Ranges B, C and D
  • 1111 Ranges A, B, C, and D

All other values are reserved. Intel recommends that the completion timeout mechanism expire in no less than 10 ms.

Disable completion timeout

On/Off

On

Disables the completion timeout mechanism. When On, the core supports the completion timeout disable mechanism via the PCI Express Device Control Register 2. The Application Layer logic must implement the actual completion timeout mechanism for the required ranges.

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