Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
Document Table of Contents

6.6. Power Management Capability Structure

Figure 46. Power Management Capability Structure - Byte Address Offsets and Layout
Table 54.  Power Management Capabilities Register - 0x078

Bits

Register Description

Default Value

Access

[31:19] Not Implemented RO 0
[18:16] Version ID: Version of Power Management Capability RO 0x3
[15:8] Next Capability Pointer: Points to the PCI Express Capability. RO 0x80
[7:0] Capability ID assigned by PCI-SIG. RO 0x01
Table 55.  Power Management Control and Status Registers - 0x07C

Bits

Register Description

Default Value

Access

[31:4] Not implemented. RO 0
[3] No Soft Reset: If set, the Function maintains its internal state when in the D3hot state. Software is not required to re-initialize the registers when the Function returns from D3hot to D0. RO Set inPlatform Designer
[2] Reserved. RO 0
[1:0] Indicates the power state of this Function. The only allowed settings are 2'b00 (D0) and 2b'11 . RW 0

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