Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

ID 683686
Date 1/11/2022
Document Table of Contents

5.12. Local Management Interface (LMI) Signals

Use the LMI interface to write log error descriptor information in the TLP header log registers. The LMI access to other registers is intended for debugging, not normal operation.
Figure 33. Local Management Interface

The LMI provides access to many of the configuration registers of the Physical and Virtual Functions. You can read all PF and Configuration Registers. You can write fields designated as RW.

Table 34.  LMI Interface






Data outputs. Valid when lmi_ack_apphas been asserted.



Read enable input.



Write enable input.



Acknowledgment for a read or write operation. The SR-IOV Bridge asserts this output for one cycle after it has completed the read or write operation. For read operations, the assertion of lmi_ack also indicates the presence of valid data on .



Byte address of 32-bit configuration register. Bits [1:0] are not used.

lmi_pf_num_app[<n>-1:0] Input

Specifies the Function number corresponding to the LMI access, Used only when the LMI access is to a Configuration register in the SR-IOV Bridge. When the Function is a VF, this input specifies the PF Number to which the VF is attached.

<n> is the number of PFs.

lmi _vf_active Input

Indicates that the Function to be accessed is a Virtual Function. When this input is asserted, the VF number offset of the Function must be provided on lmi_vf_num.

lmi _vf_num[<n>-1:0] Input

When lmi _vf_active is asserted, this input identifies the VF number offset of the Function being accessed. Its value ranges from 0-(<n>-1), where <n> is the number of VFs in the set of VFs attached to the associated PF.

<n> is the number of VFs.



Data inputs.

Figure 34. LMI Read
Figure 35. LMI Write The following figure illustrates the LMI write. Only writable configuration bits are overwritten by this operation. Read-only bits are not affected..