Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

ID 683686
Date 1/11/2022
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5.9. Configuration Extension Bus (CEB) Interface

The Configuration Extension Bus (CEB) interface provides a way to add extra capabilities on top of those available in the internal configuration space of the SR-IOV Bridge. The configuration TLPs with a destination address not matching with internally implemented registers are routed to the CEB interface. When a transaction is presented on this interface, the user application is responsible for acknowledging the request by asserting ceb_ack if it is intended or supported. For read requests, ceb_ack and ceb_din should be driven by the user logic. For write requests, only ceb_ack is needed. The bridge will return a Completion with no data upon receiving the acknowledgment.

If the user application does not implement the register at the address targeted by this interface, meaning ceb_ack will not be asserted, there will be an acknowledgment timeout, which results in a Completion with all zeros in the data and completion status fields being sent back to the host. This behavior applies for both read and write accesses.

The SR-IOV bridge sends the dword address of the register being accessed on the CEB interface with the additional function number information. This information is held on the address and data busses until an acknowledgement is received from the user application logic.

Note: Intel recommends that you select an open space in the configuration space across all available PFs or VFs by disabling optional Capabilities structures to implement the user capabilities registers. This implies that developing user registers for individual PFs or VFs is not an option.

The user application must return an acknowledgement within the number of clock cycles specified by the CEB REQ to ACK latency parameter described in section 3.3.

Table 32.   Configuration Extension Bus (CEB) Interface






When asserted, indicates a valid Configuration Extension Interface access cycle. Deasserted when ceb_ack is asserted.



Application asserts this signal for one clock cycle to acknowledge ceb_req.



Dword address of the register being accessed.



The Physical Function (PF) number of the register access.
ceb_vf_num[10:0] Output

Indicates the child Virtual Function (VF) number of the parent PF indicated by ceb_pf_num.

ceb_vf_active Output

Indicates the access is for a Virtual Function implemented in the slot's Physical Function.

ceb_din[31:0] Input

Application returns data for a read access using this signal bus.

The data must be valid when ceb_ack is asserted.

ceb_dout[31:0] Output Write data for a write access.
ceb_wr[3:0] Output

Indicates the configuration register access type (read or write). For writes, ceb_wr[3:0] also indicates the byte enables. The following encodings are defined:

4'b0000: Read

4'b0001: Write byte 0

4'b0010: Write byte 1

4'b0100: Write byte 2

4'b1000: Write byte 3

4'b1111: Write all bytes.

Combinations of byte enables (for example,4'b0101) are also valid.

The figure below shows the timing diagram for 2 write commands.

The first command sends a write for all four bytes of the register located at address = 4. ceb_vf_active being low indicates this access is for a Physical Function.

The second command sends a write for byte3 and byte2 of the register located at address = 8. ceb_vf_active being high indicates this access is for a Virtual Function.

Figure 28. Write for a Physical Function Followed by a Write for a Virtual Function

The figure below shows the timing diagram for back-to-back writes followed by a read.

The first command sends a write for all four bytes of the register located at address = 4.

The second command sends a write for byte3 and byte2 of the same register.

The third command sends a read for the same register. Note that the data returned is 5621. The upper two bytes were modified by the second write.

Figure 29. Back-to-back Writes Followed by a Read for a Physical Function