Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
Document Table of Contents

2.4. Compiling and Simulating the Design for SR-IOV

Figure 6. Procedure

Follow these steps to compile and simulate the design:

  1. Change the simulation directory.
  2. Run the simulation script for the simulator of your choice. Refer to the table below.
  3. Analyze the results.
    Table 7.  Steps to Run Simulation
    Simulator Working Directory Instructions
    Mentor ModelSim* <example_design>/top_tb/top_tb/sim/mentor/
    1. Invoke vsim
    2. do msim_setup.tcl
    3. ld_debug
    4. run -all
    5. A successful simulation ends with the following message, "Simulation stopped due to successful completion! Simulation passed."
    Mentor VCS* <example_design>/top_tb/top_tb/sim/synopsys/vcs
    1. sh vcs_setup.sh USER_DEFINED_SIM_OPTIONS=""
    2. A successful simulation ends with the following message, "Simulation stopped due to successful completion! Simulation passed."
    Cadence NCSim* <example_design>top_tb/top_tb/sim/cadence
    1. Create a shell script, my_setup.sh. This script allows you to add additional commands and override the defaults included in ncsim_setup.sh.
    2. Include the following command in my_setup.sh: source ncsim_setup.sh USER_DEFINED_SIM_OPTIONS=""
    3. chmod +x *.sh
    4. ./my_setup.sh
    5. A successful simulation ends with the following message, "Simulation stopped due to successful completion! Simulation passed."

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