2.2. Design Components for the SR-IOV Design Example
The testbench includes a PCIe Root Port BFM and a PCIe Gen3 x8 Endpoint implemented in hard logic. The SR-IOV bridge, implemented in soft logic, drives memory writes and reads to the four VFs. The simulation includes the following stages:
- Link Training
- Memory writes to each VF
- Memory reads and compares to the expected data
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