Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
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2.2. Design Components for the SR-IOV Design Example

Figure 4.  Platform Designer Testbench for Intel® Arria® 10 Gen1 x8 128-bit SR-IOV Design Example
Figure 5.  Platform Designer Schematic for TopThis image of the Intel® Arria® 10 PCI Express DMA Design Example shows only the Avalon-ST, clock, and reset interfaces.

The testbench includes a PCIe Root Port BFM and a PCIe Gen3 x8 Endpoint implemented in hard logic. The SR-IOV bridge, implemented in soft logic, drives memory writes and reads to the four VFs. The simulation includes the following stages:

  • Link Training
  • Configuration
  • Memory writes to each VF
  • Memory reads and compares to the expected data

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