Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
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2.3. Generating the SR-IOV Design Example

After installing the Quartus® Prime software, copy the design examples from the <install_dir>/ip/altera/ altera_pcie/altera_pcie_a10_ed/example_design/a10 directory. This walkthrough uses the sriov2_top_target_gen3x8_1pf_4vf.qsys design example. To run the simulation, you must rename the design example top.qsys
  1. Launch Platform Designer and open top.qsys.
  2. On the Generate menu, select Generate Testbench System.
  3. For Create testbench Platform Designer system, select Standard, BFMs for stand Platform Designer interfaces.
  4. For Create testbench simulation model, select either Verilog or VHDL.
  5. For Output Directory > Testbench, you can accept the default directory or modify it.
  6. Click Generate.
    Note: Intel® Arria® 10 devices do not support the Create timing and resource estimates for third-party EDA synthesis tools option on the Generate > Generate HDL menu. You can select this menu item, but generation fails.

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