Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
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5.11. Control Shadow Interface

The Control Shadow interface provides access to the current settings of some of the VF Control Register fields in the PCI and PCI Express Configuration Spaces in the SR-IOV Bridge. Use this interface in one of two ways.

  • To monitor specific VF registers for changes: When the Root Port performs a Configuration Write to any of the specified register fields provides the new values and the VF number. The monitor must copy the new register values as they appear on the interface and save them for future use.
  • To monitor all VF registers for changes: Assert the ctl_shdw_req_all input to request a complete scan of the register fields being monitored for all active VFs. When ctl_shdw_req_all is asserted, the SR-IOV Bridge cycles through each VF and provides the current values of the specified register fields. If a Configuration Write occurs during a scan, the SR-IOV Bridge interrupts the scan and outputs the new settings for the targeted VF. It then resumes the scan, continuing sequentially from the VF that was updated.
Table 33.   Control Shadow Interface Use this to access the control register fields of the VFs.

Signal

Direction

Description

ctl_shdw_update

Output

The SR-IOV Bridge asserts this output for one clock cycle when there is an update to one or more of the register fields being monitored. The ctl_shdw_cfg outputs drive the new values. ctl_shdw_pf_num, ctl_shdw_vf_num, and ctl_shdw_vf_active identify the VF and its PF.

ctl_shdw_pf_num[<n>-1:0]

Output

Identifies the PF whose register settings are on the ctl_shdw_cfg outputs. When the Function is a VF, this input specifies the PF Number to which the VF is attached.

ctl_shdw _vf_active

Output

When asserted, indicates that the Function whose register settings are on the ctl_shdw_cfgoutputs is a VF. ctl_shdw_vf_num drives the VF number offset.

ctl_shdw_vf_num[10:0]

Output

Identifies the VF number offset of the VF whose register settings are on ctl_shdw_cfg outputs when ctl_shdw _vf_active is asserted, Its value ranges from 0-<n>-1, where <n> is the number of VFs in the set of VFs attached to the associated PF.
ctl_shdw_cfg[6:0] Output

When ctl_shdw_updateis asserted, this output provides the current settings of the register fields of the associated Function. The bit assignments are as follows:

  • [0]: Bus Master Enable field, bit[2] of the PCI Command Register
  • [1]: MSI-X Function Mask field, bit[14] of the MSI-X Message Control Register
  • [2]: MSIX Enable field, bit[15] of the MSIX Message Control Register
  • [4:3]: TPH ST Mode Select field, bits[1:0] of TPH Requester Control Register
  • [5]: TPH Requester Enable field, bit [8] of TPH Requester Control Register
  • [6]: Enable field, bit [15] of the ATS Control Register
ctl_shdw_req_all Input

When asserted, requests a complete scan of the register fields being monitored for all active Functions. The SR-IOV Bridge cycles through each Function and provides the current settings of the register fields of each Function in sequence on ctl_shdw_cfg[6:0]. If a Configuration Write occurs during a scan, the SR-IOV Bridge interrupts the scan and outputs the new settings for the targeted VF. It then resumes the scan, continuing sequentially from the VF that was updated.

The SR-IOV Bridge checks the state of ctl_shdw_req_all at the end of each scan cycle. It starts a new scan cycle if this input is asserted.

Connect this input to logic 1 to scan the Functions continuously.

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