Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
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3.6. Intel® Arria® 10 Interrupt Capabilities

Table 13.  MSI and MSI-X Interrupt SettingsEach Physical Function defines its own MSI-X table settings. The VF MSI-X table settings are the same for all the Virtual Functions associated with each Physical Function.

Parameter

Value

Description

MSI Interrupt Settings
PF0 MSI Requests - PF3 MSI Requests 1,2,4,8,16,32

Specifies the maximum number of MSI messages the Application Layer can request. This value is reflected in Multiple Message Capable field of the Message Control register, 0x050[31:16]. For MSI Interrupt Settings, if the PF MSI option is enabled, all PFs support MSI capability.

MSI-X PF0 - MSI-X PF3 Interrupt Settings

PF MSI-X

On/Off

When On, enables the MSI-X functionality. For PF and VF MSI-X Interrupt Settings, if PF MSI-X is enabled, all PFs supports MSI-X capability.

VF MSI-X

On/Off

Bit Range

MSI-X Table size

[10:0]

System software reads this field to determine the MSI-X Table size <n>, which is encoded as <n–1>. For example, a returned value of 2047 indicates a table size of 2048. This field is read-only. Legal range is 0–2047 (211).

Address offset: 0x068[26:16]

MSI-X Table Offset

[31:0]

Specifies the offset from the BAR indicated in theMSI-X Table BAR Indicator. The lower 3 bits of the table BAR indicator (BIR) are set to zero by software to form a 32-bit qword-aligned offset 2. This field is read-only.

MSI-X Table BAR Indicator

[2:0]

Specifies which one of a function’s BAR number. This field is read-only. For 32-bit BARs, the legal range is 0–5. For 64-bit BARs, the legal range is 0, 2, or 4.

MSI-X Pending Bit Array (PBA) Offset

[31:0]

Points to the MSI-X Pending Bit Array table. It is offset from the BAR value indicated in MSI-X Table BAR Indicator. The lower 3 bits of the PBA BIR are set to zero by software to form a 32-bit qword-aligned offset. This field is read-only.

MSI-X PBA BAR Indicator

[2:0]

Specifies which BAR number contains the MSI-X PBA. For 32-bit BARs, the legal range is 0–5. For 64-bit BARs, the legal range is 0, 2, or 4. This field is read-only.

Legacy Interrupts
PF0 - PF3 Interrupt Pin inta–intd Applicable for PFs only to support legacy interrupts. When enabled, the core receives interrupt indications from the Application Layer on its INTA_IN, INTB_IN, INTC_IN and INTD_IN inputs, and sends out Assert_INTx or Deassert_INTx messages on the link in response to their activation or deactivation, respectively.

You can configure the Physical Functions with separate interrupt pins. Or, both functions can share a common interrupt pin.

PF0 - PF3 Interrupt Line 0-255

Defines the input to the interrupt controller (IRQ0 - IRQ15) in the Root Port that is activated by each Assert_INTx message.

2 Throughout this user guide, the terms word, dword and qword have the same meaning that they have in the PCI Express Base Specification. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.

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