Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
Document Table of Contents

6.16.2. ARI Enhanced Capability Header

Table 74.  ARI Enhanced Capability ID - 0x160 0x178

Bits

Register Description

Default Value

Default Value

Access

[15:0]

PCI Express Extended Capability ID for ARI.

0x000E

RO

[19:16]

Capability Version.

0x1

RO

[31:20]

Next Capability Pointer: The following values are possible:

  • If the number of VFs attached to this PFs is non-zero, this pointer points to the SR-IOV Capability, 0x200). Otherwise, its value is configured as follows:
    • PF0 with maximum link speed of 8.0 GT/s: Next Capability = Secondary PCIe, 0x280.
    • PF0 with maximum link speed of 2.5 or 5.0 GT/s and TPH Requester Capability: Next Capability = TPH Requester, 0x300.
    • PF0 with maximum link speed of 2.5 or 5.0 GT/s, with ATS Capability and no TPH Requester Capability : Next Capability = ATS, 0x3C0.
    • PFs 1–3 with TPH Requester Capability: Next Capability = TPH Requester, 0x300.
    • PFs 1–3 with ATS Capability: Next Capability = ATS, 0x3C0.
    • All other cases: Next Capability = 0.

See description

RO

Table 75.  ARI Enhanced Capability Header and Control Register - 0x164

Bits

Register Description

Default Value

Access

[0]

Specifies support for arbitration at the Function group level. Not implemented.

0

RO

[7:1] Reserved.

0

RO

[15:8]

ARI Next Function Pointer. Pointer to the next PF.

1

RO

[31:16]

Reserved.

0

RO

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