Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
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5.14. Hard IP Reconfiguration Interface

The Hard IP reconfiguration interface is an Avalon-MM slave interface with a 10‑bit address and 16‑bit data bus. You can use this bus to dynamically modify the value of configuration registers that are read-only at run time. To ensure proper system operation, reset or repeat device enumeration of the PCI Express link after changing the value of read‑only configuration registers of the Hard IP.

Table 38.  Hard IP Reconfiguration Signals

Signal

Direction

Description

hip_reconfig_clk

Input

Reconfiguration clock. The frequency range for this clock is 100–125 MHz.

hip_reconfig_rst_n

Input

Active-low Avalon-MM reset. Resets all of the dynamic reconfiguration registers to their default values as described in Hard IP Reconfiguration Registers.

hip_reconfig_address[9:0]

Input

The 10‑bit reconfiguration address.

hip_reconfig_read

Input

Read signal. This interface is not pipelined. You must wait for the return of the hip_reconfig_readdata[15:0] from the current read before starting another read operation.

hip_reconfig_readdata[15:0]

Output

16‑bit read data. hip_reconfig_readdata[15:0] is valid on the third cycle after the assertion of hip_reconfig_read.

hip_reconfig_write

Input

Write signal.

hip_reconfig_writedata[15:0]

Input

16‑bit write model.

hip_reconfig_byte_en[1:0]

Input

Byte enables, currently unused.

ser_shift_load

Input

You must toggle this signal once after changing to user mode before the first access to read‑only registers. This signal should remain asserted for a minimum of 324 ns after switching to user mode.

interface_sel

Input

A selector which must be asserted when performing dynamic reconfiguration. Drive this signal low 4 clock cycles after the release of ser_shif t_load.

Figure 37. Hard IP Reconfiguration Bus Timing of Read-Only Registers

For a detailed description of the Avalon-MM protocol, refer to the Avalon Memory Mapped Interfaces chapter in the Avalon Interface Specifications.

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