Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
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10.2. Recommended Reset Sequence to Avoid Link Training Issues

Successful link training can only occur after the FPGA is configured. Designs using CvP for configuration initially load the I/O ring and periphery image. Intel® Arria® 10 devices include a Nios II Hard Calibration IP core that automatically calibrates the transceivers to optimize signal quality after CvP completes and before entering user mode. Link training occurs after calibration. Refer to Reset Sequence for Hard IP for PCI Express IP Core and Application Layer for a description of the key signals that reset, control dynamic reconfiguration, and link training.

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