Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
Document Table of Contents

6.3.1. Type 0 Configuration Space Registers

Figure 43. Type 0 Configuration Space Registers - Byte Address Offsets and LayoutEndpoints store configuration data in the Type 0 Configuration Space.
Table 44.  Correspondence Configuration Space Capability Structures and PCIe Base Specification DescriptionThe following table lists the appropriate section of the PCI Express Base Specification that describes these registers. Refer to the PCI Express Base Specification for more information.
Byte Address

0x000

Device ID Vendor ID

Type 0 Configuration Space Header

0x004

Status Command

Type 0 Configuration Space Header

0x008

Class Code Revision ID

Type 0 Configuration Space Header

0x00C

0x00 Header Type 0x00 Cache Line Size

Type 0 Configuration Space Header

0x010

Base Address 0

Base Address Registers (Offset 10h - 24h)

0x014

Base Address 1

Base Address Registers (Offset 10h - 24h)

0x018

Base Address 2

Base Address Registers (Offset 10h - 24h)

0x01C

Base Address 3

Base Address Registers (Offset 10h - 24h)

0x020

Base Address 4

Base Address Registers (Offset 10h - 24h)

0x024

Base Address 5

Base Address Registers (Offset 10h - 24h)

0x028

Reserved

0x02C

Subsystem Device ID Subsystem Vendor ID

Type 0 Configuration Space Header

0x030

Reserved

0x034

Capabilities PTR

Type 0 Configuration Space Header

0x038

Reserved

Type 0 Configuration Space Header

0x03C

0x00 Interrupt Pin Interrupt Line

Type 0 Configuration Space Header

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