Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
Document Table of Contents

6.16.6. Page Size Registers

Table 83.  Supported Page Size Register - 0x21C

Bits

Register Description

Default Value

Access

[31:0]

Supported Page Sizes. Specifies the page sizes supported by the device

Set in Platform Designer

RO

Table 84.  System Page Size Register - 0x220

Bits

Register Description

Default Value

Access

[31:0]

Supported Page Sizes. Specifies the page size currently in use.

Set in Platform Designer

RO

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