Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
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5.9.1.2. VPD Capability Implementation

Here are the required settings if you choose to implement the VPD capability in the MSI capability register space for the physical function:
  1. Make sure the MSI feature is disabled in the IP Parameter Editor GUI.
  2. Check the Enable PCI Express Extended Space (CEB) option and specify the CEB REQ to ACK latency (in Clock Cycles).
  3. Set the CEB PF External Standard Capability Pointer Address (DW address in Hex) value to 0x14 and leave CEB PF External Extended Capability Pointer Address (DW address in Hex) in the default setting, 0x0.
Note: Table 6.2 uses byte addresses while the IP Parameter Editor GUI requires the external capability pointer address in dword format. To convert byte addresses to dword addresses, divide the byte address by 4.

Consequently, the VPD Capability register can be accessed by the host system starting from 0x50 (byte address) or 0x14 (dword address). The VPD capability structure is shown in the figure below.

The figure below shows the capability link list for this implementation:

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