Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
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6.16.3. SR-IOV Enhanced Capability Registers

Table 76.   SR-IOV Extended Capability Header Register - 0x200

Bits

Register Description

Default Value

Access

[15:0]

PCI Express Extended Capability ID

0x0010

RO

[19:16] Capability Version 1

RO

[31:16]

Next Capability Pointer: The value depends on data rate. If the number of VFs attached to this PFs is non-zero, this pointer points to the SR-IOV Extended Capability, 0x200. Otherwise, its value is configured as follows:

  • PF0 has a maximum link speed of 8.0 GT/s: Next Capability = Secondary PCIe, 0x280.
  • PF0 has a maximum link speed of 2.5 or 5.0 GT/s and TPH Requester Capability: Next Capability = TPH Requester, 0x300.
  • PF0 has a maximum link speed of 2.5 or 5.0 GT/s, with ATS Capability and no TPH Requester Capability : Next Capability = ATS, 0x3C0.
  • PFs 1–3 with TPH Requester Capability: Next Capability = TPH Requester,0x300.
  • PFs 1–3 with ATS Capability: Next Capability = ATS, 0x3C0.
  • All other cases: Next Capability = 0.

Set in Platform Designer

RO

Table 77.  SR-IOV Capabilities Register - 0x204

Bits

Register Description

Default Value

Access

[0]

VF Migration Capable

0

RO

[1] ARI Capable Hierarchy Preserved 1, for the lowest-numbered PF with SR-IOV Capability; 0 for other PFs.

RO

[31:2]

Reserved

0

Default Value

RO

Table 78.  SR-IOV Control and Status Registers - 0x208

Bits

Register Description

Default Value

Access

[0]

VF Enable

0

RW

[1] VF Migration Enable. Not implemented. 0

RO

[2]

VF Migration Interrupt Enable. Not implemented.

0

RO

[3] VF Memory Space Enable 0 RW
[4] ARI Capable Hierarchy 0 RW, for the lowest-numbered PF with SR-IOV Capability; RO for other PFs
[15:5] Reserved 0 RO
[31:16] SR-IOV Status Register. Not implemented 0 RO

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