Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

Download
ID 683686
Date 1/11/2022
Public
Document Table of Contents

3.10. PHY Characteristics

Table 21.  PHY Characteristics

Parameter

Value

Description

Gen2 TX de-emphasis

3.5dB

6dB

Specifies the transmit de-emphasis for Gen2. Intel recommends the following settings:

  • 3.5dB: Short PCB traces
  • 6.0dB: Long PCB traces.
Requested equalization far-end TX preset Preset0-Preset9 Specifies the requested TX preset for Phase 2 and 3 far-end transmitter. The default value Preset8 provides the best signal quality for most designs.
Enable soft DFE controller IP

On

Off

When On, the PCIe Hard IP core includes a decision feedback equalization (DFE) soft controller in the FPGA fabric to improve the bit error rate (BER) margin. The default for this option is Off because the DFE controller is typically not required. However, short reflective links may benefit from this soft DFE controller IP.

This parameter is available only for Gen3 mode. It is not supported when CvP or autonomous modes are enabled.

Enable RX-polarity inversion in soft logic

On

Off

This parameter mitigates the following RX-polarity inversion problem. When the Intel® Arria® 10 Hard IP core receives TS2 training sequences during the Polling.Config state, when you have not enabled this parameter, automatic lane polarity inversion is not guaranteed. The link may train to a smaller than expected link width or may not train successfully. This problem can affect configurations with any PCIe* speed and width. When you include this parameter, polarity inversion is available for all configurations except Gen1 x1. This fix does not support CvP or autonomous mode.

Did you find the information on this page useful?

Characters remaining:

Feedback Message