Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
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6.7. PCI Express Capability Structure

Figure 47. PCI Express Capability Structure - Byte Address Offsets and LayoutIn the following table showing the PCI Express Capability Structure, registers that are not applicable to a device are reserved.
Table 56.  PCI Express Capability Register - 0x080
Bits Description Default Value Access
[31:19] Reserved 0 RO
[18:16] Version ID: Version of Power Management Capability. 0x3 RO
[15:8] Next Capability Pointer: Points to the PCI Express Capability. 0x80 RO
[7:0] Capability ID assigned by PCI-SIG. 0x01 RO
Table 57.   PCI Express Device Capabilities Register -0x084
Bits Description Default Value Access
[2:0] Maximum Payload Size supported by the Function. Can be configured as 000 (128 bytes) or 001 (256 bytes) Set in Platform Designer RO
[4:3] Reserved 0 RO
[5] Extended tags supported Set in Platform Designer RO
[8:6] Acceptable L0S latency Set in Platform Designer RO
[11:9] Acceptable L1 latency Set in Platform Designer RO
[14:12] Reserved 0 RO
[15] Role-Based error reporting supported 1 RO
[17:16] Reserved 0 RO
[27:18] Captured Slot Power Limit Value and Scale: Not implemented 0 RO
[28] FLR Capable. Indicates that the device has FLR capability Set in Platform Designer RO
[31:29 ] Reserved 0 RO
Table 58.   PCI Express Device Control and Status Register - 0x088
Bits Description Default Value Access
[0] Enable Correctable Error Reporting. 0 RW
[1] Enable Non-Fatal Error Reporting. 0 RW
[2] Enable Fatal Error Reporting. 0 RW
[3] Enable Unsupported Request (UR) Reporting. 0 RW
[4] Enable Relaxed Ordering. Set in Platform Designer RW
[7:5] Maximum Payload Size. 0 (128 bytes) RW
[8] Extended Tag Field Enable. 0 RW
[10:9] Reserved. 0 RO
[11] Enable No-Snoop. 1 RW
[14:12] Maximum Read Request Size. 2 (512 bytes) RW
[15] Function-Level Reset. Writing a 1 generates a Function-Level Reset for this Function if the FLR Capable bit of the Device Capabilities Register is set. This bit always reads as 0. 0 RW
[16] Correctable Error detected. 0 RW1C
[17] Non-Fatal Error detected. 0 RW1C
[18] Fatal Error detected. 0 RW1C
[19] Unsupported Request detected. 0 RW1C
[20] Reserved. 0 RO
[21] Transaction Pending: Indicates that a Non- Posted request issued by this Function is still pending. 0 RO
[31:22] Reserved. 0 RO
Table 59.  Link Capabilities Register - 0x08C
Bits Description Default Value Access
[3:0] Maximum Link Speed 1: 2.5 GT/s

2: 5.0 GT/s

3: 8.0 GT/s

RO
[9:4] Maximum Link Width 1, 2, 4 or 8 RO
[10] ASPM Support for L0S state Set in Platform Designer RO
[11] ASPM Support for L1 state Set in Platform Designer RO
[14:12] L0S Exit Latency Set in Platform Designer, 0x6 RO
[17:15] L1 Exit Latency Set in Platform Designer, 0x0 RO
[21:18] Reserved 0 RO
[22] ASPM Optionality Compliance 1 RO
[31:23] Reserved 0 RO
Table 60.   Link Control and Status Register - 0x090
Bits Description Default Value Access
[1:0] ASPM Control 0 RW
[2] Reserved 0 R O
[3] Read Completion Boundary 0 RW
[5:4] Reserved 0 RO
[6] Common Clock Configuration 0 RW
[7] Extended Synch 0 RW
[15:8] Reserved 0 RO
[19:16] Negotiated Link Speed 0 RO
[25:20] Negotiated Link Width 0 RO
[27:26] Reserved 0 RO
[28] Slot Clock Configuration Set in Platform Designer RO
[31:29] Reserved 0 RO
Table 61.   PCI Express Device Capabilities 2 Register - 0x0A4
Bits Description Default Value Access
[3:0] Completion Timeout ranges Set in Platform Designer RO
[4] Completion Timeout disable supported Set in Platform Designer RO
[31:5] Reserved 0 RO
Table 62.   PCI Express Device Control 2 and Status 2 Register - 0x0A8
Bits Description Default Value Access
[3:0] Completion Timeout value 0xF RW
[4] Completion Timeout disable 1 RW
[5] Reserved 0 RO
[6] Atomic Operation Requester Enable 0 RW
[31:7] Reserved 0 RO
Table 63.   Link Capabilities 2 Register - 0x0AC
Bits Description Default Value Access
[0] Reserved 0 RO
[3:1] Link speeds supported

1 (2.5 GT/s)

3 (5.0 GT/s)

7 (8.0 GT/s)

Set in Platform Designer
RO
[31:4] Reserved 0 RO
Table 64.  Link Control 2 and Status 2 Register - 0x0B0
Bits Description Default Value Access
[3:0] Target Link Speed

1: Gen1

2: Gen2

3: Gen3

RWS
[4] Enter Compliance 0 RWS
[5] Hardware Autonomous Speed Disable 0 RW
[6] Selectable De-emphasis 0 RO
[9:7] Transmit Margin 0 RWS
[10] Enter Modified Compliance 0 RWS
[11] Compliance SOS 0 RWS
[15:12] Compliance Preset/De-emphasis 0 RWS
[16] Current De-emphasis Level 0 RO
[17] Equalization Complete 0 RO
[18] Equalization Phase 1 Successful 0 RO
[19] Equalization Phase 2 Successful 0 RO
[20] Equalization Phase 3 Successful 0 RO
[21] Link Equalization Request 0 RW1C
[31:22] Reserved 0 RO

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