Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
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5.5. Configuration Status Interface

The output signals listed below drive the settings of the various configuration register fields of the Functions. These settings are often needed in designing Application Layer logic.

Table 26.  Configuration Status Interface

Signal

Direction

Description

bus_num_f0-f3[7:0] Output

Bus number assigned to the PF by the Root Complex. Captured from CfgWr transactions.

When ARI is in use, the Application Layer uses bus_num_f<n>-1 to generate requests as a master or respond to requests as a Completer.

When ARI is not in use, the application uses bus_num_f<n>-1 when generating requests from PF<n>-1 and its associated VF and responding to requests as a Completer.

Provided for information only. The SR-IOV Bridge inserts the appropriate bus number in the header of transmitted TLPs
device_num_f0-f3[4:0] Output

Device number assigned to the PF by the Root Complex. Captured from CfgWr transactions. When ARI is not in use, the Application Layer uses device_num_f<n>-1 when generating requests from PF<n>-1 and responding to requests as a Completer.

Not used when ARI is enabled.

Provided for information only. The SR-IOV Bridge inserts the appropriate device number in the header of transmitted TLPs.

mem_space_en_pf[<n>-1:0]

Output

The PF Command Registers drive the Memory Space Enable bit. <n> is the number of PFs.

bus_master_en_pf[<n>-1:0]

Output

The PF Command Registers drive the Bus Master Enable bit. <n> is the number of PFs.

mem_space_en_vf[<n>-1:0]

Output

The PF Control Registers drive the SR-IOV Memory Space Enable bit. <n> is the number of PFs.

pf[<n>-1:0]_num_vfs[15:0]

Output

This output drives the value of the NumVFs register in the PF SR-IOV Capability Structure .

max_payload_size[2:0]

Output

When only PF0 is present, the max payload size field of the PF0 PCI Express Device Control Register drives this output. When more PFs are present, the minimum value of the max payload size field of the PCI Express Device Control Registers drives this output.

rd_req_size[2:0]

Output

When only PF 0 is present, the max read request size field of PF0 PCI Express Device Control Register drives this output. When more PFs are present, the minimum value of the max read request size fields of the PCI Express Device Control Registers drives this output.

extended_tag_en_pf[<n>-1:0] Output Bit <n>of this output reflects the setting of the Extended Tag Enable, bit[8], of the Device Control Register of PF<n>.
completion_timeout_ disable_pf[<n>-1:0]   Bit <n> of this output reflects the setting of the Completion Timeout Disable, bit [4], of the Device Control 2 Register of PF<n>.
atomic_op_requester_en_pf[<n>-1:0] Output Bit <n> of this output reflects the setting of the Atomic Op Requester Enable bit of the Device Control 2 Register of PF <n>.
tph_st_mode_pf[2*<n>-1:0] Output Bits [1:0] of this output reflect the setting of the TPH ST Mode Select field, bits[1:0] of the TPH Requester Control Register of PF0. Bits [3:2] reflect the setting of the TPH ST Mode Select field bits [1:0] of the TPH Requester Control Register of PF 1, and so on.
tph_requester_en_pf[<n>-1:0] Output Bit <n>of this output reflects the setting of the TPH Requester Enable field, bit[8], of the TPH Requester Control Register of PF <n>.
ats_stu_pf[5*<n>-1:0] Output Bits [4:0] of this output reflect the setting of the Smallest Translation Unit field, bits [4:0], in the ATS Control Register of PF0; bits [9:5] reflect the setting of the Smallest Translation Unit field, bits [4:0], in the ATS Control Register of PF1, and so on.
ats_en_pf[<n>-1:0] Output Bit <n>of this output reflects the setting of the Enable bit, bit [15], in the ATS Control Register of PF <n>.

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