Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

Download
ID 683686
Date 1/11/2022
Public
Document Table of Contents

6.15. Header Log Registers 0-3

Table 72.  Header Log Registers 0-3 - 0x11C - 0x128

This register contains the first 4 bytes of a TLP header captured from the link on detection of an uncorrectable error. Byte 0 (Type/Format field) of the header is stored in bit positions [31:24].

Bits

Register Description

Default Value

Access

[31:0]

First 4 bytes of captured TLP header

0

ROS

Did you find the information on this page useful?

Characters remaining:

Feedback Message