Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
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3.1. Parameters

This chapter provides a reference for all the parameters of the IP core.
Table 8.  Design Environment ParameterStarting in Intel® Quartus® Prime 18.0, there is a new parameter Design Environment in the parameters editor window.

Parameter

Value

Description

Design Environment

Standalone

System

Identifies the environment that the IP is in.

  • The Standalone environment refers to the IP being in a standalone state where all its interfaces are exported.
  • The System environment refers to the IP being instantiated in a Platform Designer system.
Table 9.  System Settings

Parameter

Value

Description

Application Interface Type

Avalon-ST

Avalon-MM

Avalon-MM with DMA

Avalon-ST with SR-IOV

Selects the interface to the Application Layer.

Note: When the Design Environment parameter is set to System, all four Application Interface Types are available. However, when Design Environment is set to Standalone, only Avalon-ST and Avalon-ST with SR-IOV are available.
Hard IP mode

Gen3x8, Interface: 256-bit, 250 MHz

Gen3x4, Interface: 256-bit, 125 MHz

Gen3x4, Interface: 128-bit, 250 MHz

Gen3x2, Interface: 128-bit, 125 MHz

Gen3x2, Interface: 64-bit, 250 MHz

Gen3x1, Interface: 64-bit, 125 MHz

Gen2x8, Interface: 256-bit, 125 MHz

Gen2x8, Interface: 128-bit, 250 MHz

Gen2x4, Interface: 128-bit, 125 MHz

Gen2x2, Interface: 64-bit, 125 MHz

Gen2x4, Interface: 64-bit, 250 MHz

Gen2x1, Interface: 64-bit, 125 MHz

Gen1x8, Interface: 128-bit, 125 MHz

Gen1x8, Interface: 64-bit, 250 MHz

Gen1x4, Interface: 64-bit, 125 MHz

Gen1x2, Interface: 64-bit, 125 MHz

Gen1x1, Interface: 64-bit, 125 MHz

Gen1x1, Interface: 64-bit, 62.5 MHz

Selects the following elements:

  • The lane data rate. Gen1, Gen2, and Gen3 are supported
  • The width of the data interface between the hard IP Transaction Layer and the Application Layer implemented in the FPGA fabric
  • The Application Layer interface frequency

Intel® Cyclone® 10 GX devices support up to Gen2 x4 configurations.

Port type

Native Endpoint

Root Port

Specifies the port type.

The Endpoint stores parameters in the Type 0 Configuration Space. The Root Port stores parameters in the Type 1 Configuration Space.

The Avalon-ST with SR-IOV interface supports only Native Endpoint operation.

You can enable the Root Port in the current release. Root Port mode only supports the Avalon® -MM interface type, and it only supports basic simulation and compilation. However, the Root Port mode is not fully verified.

RX Buffer credit allocation -performance for received requests

Minimum

Low

Balanced

Determines the allocation of posted header credits, posted data credits, non-posted header credits, completion header credits, and completion data credits in the 16 KB RX buffer. The settings allow you to adjust the credit allocation to optimize your system.

The credit allocation for the selected setting displays in the Message pane. The Message pane dynamically updates the number of credits for Posted, Non-Posted Headers and Data, and Completion Headers and Data as you change this selection.

Refer to the Throughput Optimization chapter for more information about optimizing your design.

Refer to the RX Buffer Allocation Selections Available by Interface Type below for the availability of these settings by interface type.

Minimum—configures the minimum PCIe specification allowed for non-posted and posted request credits, leaving most of the RX Buffer space for received completion header and data. Select this option for variations where application logic generates many read requests and only infrequently receives single requests from the PCIe link.

Low—configures a slightly larger amount of RX Buffer space for non-posted and posted request credits, but still dedicates most of the space for received completion header and data. Select this option for variations where application logic generates many read requests and infrequently receives small bursts of requests from the PCIe link. This option is recommended for typical endpoint applications where most of the PCIe traffic is generated by a DMA engine that is located in the endpoint application layer logic.

Balanced—configures approximately half the RX Buffer space to received requests and the other half of the RX Buffer space to received completions. Select this option for variations where the received requests and received completions are roughly equal.

RX Buffer completion credits

Header credits

Data credits

Displays the number of completion credits in the 16 KB RX buffer resulting from the credit allocation parameter. Each header credit is 16 bytes. Each data credit is 20 bytes.

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