Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

ID 683686
Date 1/11/2022
Document Table of Contents

9.5. Intel® Arria® 10 Hard IP for PCI Express with Single-Root I/O Virtualization (SR-IOV)

The Intel® Arria® 10 Hard IP for PCI Express with SR-IOV bypasses the Configuration Space and base address register (BAR) matching logic of the Hard IP. The SR-IOV bridge implements the following functions in soft logic:

  • Configuration spaces for eight PCIe Physical Functions and 2048 Virtual Functions
  • BAR checking logic
  • Interrupt generation
  • Error messages for Advanced Error Reporting (AER)
  • Address Translation Services (ATS)
  • TLP Processing Hints (TPH)
  • Control Shadow Interface to read the current settings for some of the VF Control Register fields in the PCI and PCI Express Configuration Spaces

The SR-IOV processes memory requests, Completions and messages received from the link. It passes them to the Application Layer unmodified, using the Avalon-ST RX interface. The SR-IOV Bridge does not maintain any state for requests outstanding on the Master or Target sides. The RX interface delivers Completion TLPs to the Application Layer in the same order as received from the link. It does not match Completion TLPs with the outstanding requests from the Application Layer.

The following figure illustrates the SR-IOV Bridge logic and its interfaces to the Intel® Arria® 10 Hard IP for PCI Express and Application Layer.

Figure 55. Block Diagram of the Intel® Arria® 10 Hard IP for PCI Express IP with the SR-IOV Bridge

SR-IOV Bridge Logic Details

Soft logic in the SR-IOV Bridge decodes Configuration Space transactions on Avalon-ST interface via Configuration Bypass mode and forwards them to the internal Configuration Block. The Configuration Block implements the following logic:

  • Processes incoming Configuration Space TLPs and generates Completions
  • Includes Configuration Space registers of eight Physical Functions and 2048 Virtual Functions.
  • Generates MSI, MSI-X, and Legacy Interrupts (INTx Assert and Deassert)
  • Generates error messages for AER
  • Multiplexes the following data sources to on the Avalon-ST TX interface:
    • Master-side requests and Target-side Completions generated by the Application Layer
    • UR Completions from the BAR Check block for Memory Read Requests
  • Transmits Memory Read and Memory Write received on TX Avalon-ST interface from the Application Layer. The core forwards these requests to the host as is, without any checking for errors. Application Layer logic must make sure the transmitted memory requests satisfy all PCI Express requirements.

BAR Logic Details

The BAR block includes the following functions:

  • Compares the addresses of received memory transactions to the BAR settings for the targeted function
  • Identifies PF and VF BAR accesses
  • Discards all memory transactions that are not in the address range of any of the configured BARs
  • Generates Unsupported Request (UR) Completions for requests that fail the BAR check

Local Management Interface (LMI)

SR-IOV LMI logic accesses Configuration Space Registers of all Physical and Virtual Functions. The LMI logic accepts read and write requests from the Application Layer and directs requests to either the LMI interface of the Hard IP or the Configuration Registers in the Configuration Block.