Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
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1.6. Performance and Resource Utilization

Because the PCIe protocol stack is implemented in hardened logic, it uses no core device resources (no ALMs and no embedded memory).

The SR-IOV Bridge is implemented is soft logic, requiring FPGA fabric resources. The following table shows the typical device resource utilization for selected configurations using the current version of the Quartus® Prime software. With the exception of M20K memory blocks, the numbers of ALMs and logic registers are rounded up to the nearest 50.

Table 5.  Performance and Resource Utilization Intel® Arria® 10 Avalon-ST with SR-IOV
Number of PFs and VFs

ALMs

M20K Memory Blocks

Logic Registers

1 PF, 4 VFs

2350

0

5200

2 PFs, 4 VFs

3600

0

6500

4 PFs, 4 VFs 4650 0 7700
1 PF, 2048 VFs 10350 0 5700
2 PFs, 2048 VFs 11750 0 7500
4 PFs 2048 VFs 14150 0 10650
2 PFs 2300 0 5100
4 PFs 3450 0 6300

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