Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
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6.16.1. SR-IOV Virtualization Extended Capabilities Registers Address Map

Figure 48. SR-IOV Virtualization Extended Capabilities Registers
Table 73.   SR-IOV Virtualization Extended Capabilities Registers

Byte Address Offset

Name

Description

Alternative RID (ARI) Capability Structure

0x160 ARI Enhanced Capability Header PCI Express Extended Capability ID for ARI and next capability pointer.
0x0164 ARI Capability Register, ARI Control Register The lower 16 bits implement the ARI Capability Register and the upper 16 bits implement the ARI Control Register.

Single-Root I/O Virtualization (SR-IOV) Capability Structure

0x200

SR-IOV Extended Capability Header

PCI Express Extended Capability ID for SR-IOV and next capability pointer.

0x204

SR-IOV Capabilities Register

Lists supported capabilities of the SR-IOV implementation.

0x208

SR-IOV Control and Status Registers

The lower 16 bits implement the SR-IOV Control Register. The upper 16 bits implement the SR-IOV Status Register.

0x20C

InitialVFs/TotalVFs

The lower 16 bits specify the initial number of VFs attached to PF0. The upper 16 bits specify the total number of PFs available for attaching to PF0.

0x210

Function Dependency Link, NumVFs

The Function Dependency field describes dependencies between Physical Functions. The NumVFs field contains the number of VFs currently configured for use.

0x214

VF Offset/Stride

Specifies the offset and stride values used to assign routing IDs to the VFs.

0x258

VF Device ID

Specifies VF Device ID assigned to the device.

0x21C

Supported Page Sizes

Specifies all page sizes supported by the device.

0x220

System Page Size

Stores the page size currently selected.

0x224

VF BAR 0

VF Base Address Register 0. Can be used independently as a 32-bit BAR, or combined with VF BAR 1 to form a 64-bit BAR.

0x228

VF BAR 1

VF Base Address Register 1. Can be used independently as a 32-bit BAR, or combined with VF BAR 0 to form a 64-bit BAR.

0x22C

VF BAR 2

VF Base Address Register 2. Can be used independently as a 32-bit BAR, or combined with VF BAR 3 to form a 64-bit BAR.

0x230

VF BAR 3

VF Base Address Register 3. Can be used independently as a 32-bit BAR, or combined with VF BAR 2 to form a 64-bit BAR.

0x234

VF BAR 4

VF Base Address Register 4. Can be used independently as a 32-bit BAR, or combined with VF BAR 5 to form a 64-bit BAR.

0x238

VF BAR 5

VF Base Address Register 5. Can be used independently as a 32-bit BAR, or combined with VF BAR 4 to form a 64-bit BAR.

0x23C

VF Migration State Array Offset

Not implemented.

Secondary PCI Express Extended Capability Structure (Gen3, PF 0 only)

0x280

Secondary PCI Express Extended Capability Header

PCI Express Extended Capability ID for Secondary PCI Express Capability, and next capability pointer.

0x284

Link Control 3 Register

Not implemented.

0x288

Lane Error Status Register

Per-lane error status bits.

0x28C

Lane Equalization Control Register 0

Transmitter Preset and Receiver Preset Hint values for Lanes 0 and 1 of remote device. These values are captured during Link Equalization.

0x290

Lane Equalization Control Register 1

Transmitter Preset and Receiver Preset Hint values for Lanes 2 and 3 of remote device. These values are captured during Link Equalization.

0x294

Lane Equalization Control Register 2

Transmitter Preset and Receiver Preset Hint values for Lanes 4 and 5 of remote device. These values are captured during Link Equalization.

0x298

Lane Equalization Control Register 3

Transmitter Preset and Receiver Preset Hint values for Lanes 6 and 7 of remote device. These values are captured during Link Equalization.

Transaction Processing Hints (TPH) Requester Capability Structure

0x300

TPH Requester Extended Capability Header

PCI Express Extended Capability ID for TPH Requester Capability, and next capability pointer.

0x304

TPH Requester Capability Register

PCI Express Extended Capability ID for TPH Requester Capability, and next capability pointer. This register contains the advertised parameters for the TPH Requester Capability.

0x308

TPH Requester Control Register

This register contains enable and mode select bits for the TPH Requester Capability.

Address Translation Services (ATS) Capability Structure

0x3C0

ATS Extended Capability Header

PCI Express Extended Capability ID for ATS Capability, and next capability pointer.

0x3C4

ATS Capability Register and ATS Control Register

This location contains the 16-bit ATS Capability Register and the 16-bit ATS Control Register.

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