Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
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5.6. Clock Signals

Table 27.  Clock Signals Hard IP Implementation

Signal

Direction

Description

refclk

Input

Reference clock for the Intel® Arria® 10 Hard IP for PCI Express. It must have the frequency specified under the System Settings heading in the parameter editor.

pld_clk

Input

Clocks the Application Layer. You can drive this clock with coreclkout_hip. If you drive pld_clk with another clock source, it must be equal to or faster than coreclkout.

All the interfaces and internal modules of the SR-IOV Bridge use this clock as the reference clock. Its frequency is 125 or 250 MHz.

coreclkout_hip

Output

This is a fixed frequency clock used by the Data Link and Transaction Layers. To meet PCI Express link bandwidth constraints, this clock has minimum frequency requirements as listed in coreclkout_hip Values for All Parameterizations in the Reset and Clocks chapter .

Refer to Intel® Arria® 10 Hard IP for PCI Express Clock Domains in the Reset and Clocks chapter for more information about clocks.

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