1.1. Intel® Arria® 10 Avalon® -ST Interface with SR-IOV for PCI Express* Datasheet
Intel® Arria® 10 FPGAs include a configurable, hardened protocol stack for PCI Express* that is compliant with PCI Express Base Specification 2.1 or 3.0. The Intel® Arria® 10 Hard IP for PCI Express* with Single Root I/O Virtualization (SR-IOV) IP core consists of this hardened protocol stack and the SR-IOV soft logic. The SR-IOV soft logic uses the Configuration Space Bypass mode of the Hard IP to bypass the internal configuration block and BAR matching logic. These functions are implemented in external soft logic. Soft logic in the SR-IOV Bridge also implements interrupts and error reporting.
The SR-IOV Bridge was redesigned to support up to 8 Physical Functions (PFs) and 2048 Virtual Functions (VFs). The SR-IOV bridge also supports the Address Translation Services (ATS) and TLP Processing Hints (TPH) capabilities.
PCI Express Gen2 (5.0 Gbps) - 256-bit interface
PCI Express Gen3 (8.0 Gbps) - 256-bit interface