Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

Download
ID 683686
Date 1/11/2022
Public
Document Table of Contents

3.9.2. Error Reporting

Table 17.  Error Reporting

Parameter

Value

Default Value

Description

Enable Advanced Error Reporting (AER)

On/Off

Off

When On, enables the Advanced Error Reporting (AER) capability.

Enable ECRC checking

On/Off

Off

When On, enables ECRC checking. Sets the read-only value of the ECRC check capable bit in the Advanced Error Capabilities and Control Register. This parameter requires you to enable the AER capability.

Enable ECRC generation

On/Off

Off

When On, enables ECRC generation capability. Sets the read-only value of the ECRC generation capable bit in the Advanced Error Capabilities and Control Register. This parameter requires you to enable the AER capability.

Enable ECRC forwarding on the Avalon-ST interface

On/Off

Off

When On, enables ECRC forwarding to the Application Layer. On the Avalon‑ST RX path, the incoming TLP contains the ECRC dword (1) and the TD bit is set if an ECRC exists. On the transmit the TLP from the Application Layer must contain the ECRC dword and have the TD bit set.

Track RX completion buffer overflow on the Avalon-ST interface

On/Off

Off

When On, the core includes the rxfc_cplbuf_ovf output status signal to track the RX posted completion buffer overflow status.

Note:

  1. Throughout this user guide, the terms word, dword and qword have the same meaning that they have in the PCI Express Base Specification. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits.

Did you find the information on this page useful?

Characters remaining:

Feedback Message