Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
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6.17. Virtual Function Registers

The SR-IOV Bridge implements the PCI and PCI Express Configuration Spaces for a maximum of 2048 Virtual Functions. The VF registers available are a subset of the PF registers. For example, the VFs do not implement the Link Capabilities 2 register. The definitions of VF registers are the same as PF registers. For additional details, refer to the PCI Express Base Specification 3.0.
Note: The following Virtual Function register map is applicable to all revisions of the Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe from the 18.1 release of Intel® Quartus® Prime onward.
Table 94.   Virtual Function Registers - Differences from PF

Address (hex)

Name

Description

0x000 Vendor ID and Device ID Register Vendor ID Register and Device ID Registers defined in PCI Express Base Specification 3.0 . These registers are hardwired to all 1s.
0x004 Command and Status Register PCI Command and Status Registers. Refer to Command and Status Register for VFs for descriptions of the implemented fields.
0x008 Revision ID and Class Code Register PCI Revision ID and Class Code Registers defined in PCI Express Base Specification 3.0 . The VF has the same settings and access as PF0.
0x00C BIST, Header Type, Latency Timer and Cache Line Size Registers Contains the following registers defined in the PCI Express Base Specification 3.0 : BIST Register, Header Type Register, Latency Timer, Cache Line Size Register. These registers are hardwired to all 0s for VFs.
0x010:

0x028

Reserved N/A
0x02C Subsystem Vendor ID and Subsystem ID Registers PCI Subsystem Vendor ID and Subsystem ID Registers. The VF has the same settings and access as PF0.
0x030 Reserved N/A
0x034 Capabilities Pointer This register points to the first Capability Structure in the PCI Configuration Space. For VFs, it points to the MSI-X capability.
0x038:

0x03C

Reserved N/A

MSI-X Capability Structure

0x07C

MSI-X Control Register

Contains the MSI-X Message Control Register, Capability ID for MSI-X, and the next capability pointer. The VF has the same fields and access as the parent PF.

0x080

MSI-X Table Offset

Points to the MSI-X Table in memory. Also specifies the BAR corresponding to the memory segment where the MSI-X Table resides. The VF has the same fields and access as the PF.

0x084

MSI-X PBA Offset

Points to the MSI-X Pending Bit Array in memory. Also, specifies the BAR corresponding to the memory segment where the PBA Array resides. The VF has the same fields and access as the parent PF.

PCI Express Capability Structure

0x040

PCI Express Capability List Register

Capability ID, PCI Express Capabilities Register, and the next capability pointer. Refer to cite="PCI Express Capability List Register for VFs" for descriptions of the implemented fields.

0x044

PCI Express Device Capabilities Register

PCI Express Device Capabilities Register. The VF Device Capabilities Register supports the same fields as the PF Device Capabilities Register.

0x048

PCI Express Device Control and Status Registers

The lower 16 bits implement the PCI Express Device Control Register. The upper 16 bits implement the Device Status Register. Refer to PCI Express Devices Control and Status Registers for VFs for descriptions of the implemented fields.

0x04C

Link Capabilities Register

A read to any VF with this address returns the Link Capabilities Register settings of the parent PF.

0x050

Link Control and Status Registers

This register is not implemented for VFs, and reads as all 0s.

0x054

Device Capabilities 2 Registers

A read to any VF with this address returns the Device Capabilities 2 Register settings of the parent PF.

0x058

Device Control 2 and Status 2 Registers

This register is not implemented for VFs. A read to this address returns all 0s.

0x05C

Link Capabilities 2 Register

This register is not implemented for VFs. A read to this address returns all 0s.

0x060 Link Control 2 and Status 2 Registers This register contains control and status bits for the PCIe link. For VFs, bit[16] stores the current de-emphasis level setting for the parent PF. All other bits are reserved.

Alternate RID (ARI) Capability Structure

0x100

ARI Enhanced Capability Header

PCI Express Extended Capability ID for ARI and Next Capability pointer. The Next Capability pointer points to NULL.

0x104

ARI Capability Register, ARI Control Register

This register is not implemented for VFs. A read to this address returns all 0s.

Transaction Processing Hints (TPH) Requester Capability Structure
0x300 TPH Requester Extended Capability Header PCI Express Extended Capability ID for TPH Requester Capability, and next capability pointer.
0x304 TPH Requester Capability Register This register contains the advertised parameters for the TPH Requester Capability.
0x308 TPH Requester Control Register This register contains enable and mode select bits for the TPH Requester Capability.
Address Translation Services (ATS) Capability Structure
0x3C0 ATS Extended Capability Header PCI Express Extended Capability ID for ATS Capability, and next capability pointer.
0x3C4 ATS Capability Register and ATS Control Register This location contains the 16-bit ATS Capability Register and the 16-bit ATS Control Register.
Table 95.  Command and Status Register for VFs - 0x004

Bits

Register Description

Default Value

Access

[1:0] Reserved. 0 RO
[2] Bus Master enable. When set, the VF can generate transactions as a bus master. 0 RW
[19:3] Reserved. 0 RO
[20] Indicates the presence of PCI Extended Capabilities. This bit is hardwired to 1. 1 RO
[23:21] Reserved. 0 RO
[24]
Master Data Parity Error: The device sets this bit when when the following occurs:
  • It has received a poisoned Completion directed at this VF
  • This VF has sent a poisoned memory write request on the link

This bit can only be set if the Parity Error Response Enable bit of the PCI Command Register of the parent PF is 1.

This bit is cleared by writing a 1.
0 RW1C
[26:25] Reserved. 0 RO
[27]

Signaled Target Abort: The device sets this bit when this VF has sent a Completion with the Completer Abort (CA) status to the link.

This bit is cleared by writing a 1
0 RW1C
[28]

Received Target Abort: The device sets this bit when it has received a Completion with the Completer Abort (CA) status targeting t this VF.

This bit is cleared by writing a 1
0 RW1C
[29]

Received Master Abort: The device sets this bit when it has received a Completion with the Unsupported Request (UR) status targeting this VF.

This bit is cleared by writing a 1
0 RW1C
[30]

Signaled System Error: The VF sets this bit when it has sent Fatal or Non-Fatal error message to the Root Complex. This bit can only be set if the SERR Enable bit of the PCI Command Register of the parent PF is enabled.

This bit is cleared by writing a 1.
0 RW1C
[31]

Received Master Abort: The VF sets this bit when it has received a Completion with the Unsupported Request (UR) status.

This bit is cleared by writing a 1
0 RW1C
Table 96.  PCI Express Capability List Register for VFs - 0x080

Bits

Register Description

Default Value

Access

[31:19] Hardwired to 0. 2 RO
[18:16] Version ID: Version of PCI Express Capability. 0 RW
[15:8] Next Capability Pointer: Points to NULL. 0 RO
[7:0] Capability ID assigned by PCI-SIG. 0x10 RO
Table 97.  PCI Express Device Control and Status Registers for VFs - 0x088

Bits

Register Description

Default Value

Access

Control Register

[14:0] Reserved. 0 RO
[15] Function-Level Reset. Writing a 1 to this bit generates a Function-Level Reset for this VF. Only functional when the PF Device Capabilities Register FLR Capable bit is set. This bit always reads as 0. 0 RW

Status Register

[16] Correctable Error Detected. 0 RW1C
[17] Non-Fatal Error Detected. 0 RW1C
[18] Fatal Error Detected. 0 RW1C
[19] Unsupported Request Detected. 0 RW1C
[20] Not implemented. 0 RO
[21] Transaction Pending. When set, indicates that a Non-Posted request issued by this VF is still pending. 0 RO
[31:22] Reserved. 0 RO

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