Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 9/12/2024
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Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the SR-IOV Design Example 3. Parameter Settings 4. Physical Layout 5. Interfaces and Signal Descriptions 6. Registers 7. Reset and Clocks 8. Programming and Testing SR-IOV Bridge MSI Interrupts 9. Error Handling 10. IP Core Architecture 11. Design Implementation 12. Debugging 13. Document Revision History A. Transaction Layer Packet (TLP) Header Formats B. Arria® 10 Avalon-ST with SR-IOV Interface for PCIe Solutions User Guide Archive
1. Datasheet x
1.1. Arria® 10 Avalon® -ST Interface with SR-IOV for PCI Express* Datasheet 1.2. Release Information 1.3. Device Family Support 1.4. Debug Features 1.5. IP Core Verification 1.6. Performance and Resource Utilization 1.7. Recommended Speed Grades for SR-IOV Interface
1.1. Arria® 10 Avalon® -ST Interface with SR-IOV for PCI Express* Datasheet x
1.1.1. SR-IOV Features
1.5. IP Core Verification x
1.5.1. Compatibility Testing Environment
2. Getting Started with the SR-IOV Design Example x
2.1. Directory Structure for Arria® 10 SR-IOV Design Example 2.2. Design Components for the SR-IOV Design Example 2.3. Generating the SR-IOV Design Example 2.4. Compiling and Simulating the Design for SR-IOV
3. Parameter Settings x
3.1. Parameters 3.2. Arria® 10 Avalon-ST Settings 3.3. Arria® 10 SR-IOV System Settings 3.4. Base Address Register (BAR) Settings 3.5. SR-IOV Device Identification Registers 3.6. Arria® 10 Interrupt Capabilities 3.7. Physical Function TLP Processing Hints (TPH) 3.8. Address Translation Services (ATS) 3.9. PCI Express and PCI Capabilities Parameters 3.10. PHY Characteristics 3.11. Example Designs
3.9. PCI Express and PCI Capabilities Parameters x
3.9.1. PCI Express and PCI Capabilities 3.9.2. Error Reporting 3.9.3. Link Capabilities 3.9.4. Slot Capabilities 3.9.5. Power Management
4. Physical Layout x
4.1. Hard IP Block Placement In Cyclone® 10 GX Devices 4.2. Hard IP Block Placement In Arria® 10 Devices 4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates 4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate 4.5. PCI Express Gen3 Bank Usage Restrictions
5. Interfaces and Signal Descriptions x
5.1. Avalon-ST TX Interface 5.2. Component-Specific Avalon-ST Interface Signals 5.3. Avalon-ST RX Interface 5.4. BAR Hit Signals 5.5. Configuration Status Interface 5.6. Clock Signals 5.7. Function-Level Reset (FLR) Interface 5.8. SR-IOV Interrupt Interface 5.9. Configuration Extension Bus (CEB) Interface 5.10. Implementing MSI-X Interrupts 5.11. Control Shadow Interface 5.12. Local Management Interface (LMI) Signals 5.13. Reset, Status, and Link Training Signals 5.14. Hard IP Reconfiguration Interface 5.15. Serial Data Signals 5.16. Test Signals 5.17. PIPE Interface Signals 5.18. Arria® 10 Development Kit Conduit Interface
5.9. Configuration Extension Bus (CEB) Interface x
5.9.1. Vital Product Data (VPD) Capability
5.9.1. Vital Product Data (VPD) Capability x
5.9.1.1. Determine the Pointer Address of an External Capability Register 5.9.1.2. VPD Capability Implementation
6. Registers x
6.1. Addresses for Physical and Virtual Functions 6.2. Correspondence between Configuration Space Registers and the PCIe Specification 6.3. PCI and PCI Express Configuration Space Registers 6.4. MSI Registers 6.5. MSI-X Capability Structure 6.6. Power Management Capability Structure 6.7. PCI Express Capability Structure 6.8. Advanced Error Reporting (AER) Enhanced Capability Header Register 6.9. Uncorrectable Error Status Register 6.10. Uncorrectable Error Mask Register 6.11. Uncorrectable Error Severity Register 6.12. Correctable Error Status Register 6.13. Correctable Error Mask Register 6.14. Advanced Error Capabilities and Control Register 6.15. Header Log Registers 0-3 6.16. SR-IOV Virtualization Extended Capabilities Registers 6.17. Virtual Function Registers
6.3. PCI and PCI Express Configuration Space Registers x
6.3.1. Type 0 Configuration Space Registers 6.3.2. PCI and PCI Express Configuration Space Register Content 6.3.3. Interrupt Line and Interrupt Pin Register
6.16. SR-IOV Virtualization Extended Capabilities Registers x
6.16.1. SR-IOV Virtualization Extended Capabilities Registers Address Map 6.16.2. ARI Enhanced Capability Header 6.16.3. SR-IOV Enhanced Capability Registers 6.16.4. Initial VFs and Total VFs Registers 6.16.5. VF Device ID Register 6.16.6. Page Size Registers 6.16.7. VF Base Address Registers (BARs) 0-5 6.16.8. Secondary PCI Express Extended Capability Header 6.16.9. Lane Status Registers 6.16.10. Transaction Processing Hints (TPH) Requester Enhanced Capability Header
7. Reset and Clocks x
7.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer 7.2. Function Level Reset (FLR) 7.3. Clocks
7.3. Clocks x
7.3.1. Clock Domains 7.3.2. Clock Summary
7.3.1. Clock Domains x
7.3.1.1. coreclkout_hip 7.3.1.2. pld_clk
8. Programming and Testing SR-IOV Bridge MSI Interrupts x
8.1. Setting Up and Verifying MSI Interrupts 8.2. Masking MSI Interrupts 8.3. Dropping a Pending MSI Interrupt
9. Error Handling x
9.1. Physical Layer Errors 9.2. Data Link Layer Errors 9.3. Transaction Layer Errors 9.4. Error Reporting and Data Poisoning 9.5. Uncorrectable and Correctable Error Status Bits
10. IP Core Architecture x
10.1. PCI Express Protocol Stack 10.2. Data Link Layer 10.3. Physical Layer 10.4. Top-Level Interfaces 10.5. Arria® 10 Hard IP for PCI Express with Single-Root I/O Virtualization (SR-IOV)
10.4. Top-Level Interfaces x
10.4.1. Avalon-ST Interface 10.4.2. Clocks and Reset 10.4.3. Interrupts 10.4.4. PIPE
11. Design Implementation x
11.1. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 11.2. Recommended Reset Sequence to Avoid Link Training Issues 11.3. SDC Timing Constraints
12. Debugging x
12.1. Setting Up Simulation 12.2. Simulation Fails To Progress Beyond Polling.Active State 12.3. Hardware Bring-Up Issues 12.4. Link Training 12.5. Creating a Signal Tap Debug File to Match Your Design Hierarchy 12.6. Use Third-Party PCIe Analyzer 12.7. BIOS Enumeration Issues
12.1. Setting Up Simulation x
12.1.1. Changing Between Serial and PIPE Simulation 12.1.2. Using the PIPE Interface for Gen1 and Gen2 Variants 12.1.3. Viewing the Important PIPE Interface Signals 12.1.4. Disabling the Scrambler for Gen1 and Gen2 Simulations 12.1.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
13. Document Revision History x
13.1. Document Revision History for the Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide
A. Transaction Layer Packet (TLP) Header Formats x
A.1. TLP Packet Formats without Data Payload A.2. TLP Packet Formats with Data Payload
1. Datasheet
2. Getting Started with the SR-IOV Design Example
3. Parameter Settings
4. Physical Layout
5. Interfaces and Signal Descriptions
6. Registers
7. Reset and Clocks
8. Programming and Testing SR-IOV Bridge MSI Interrupts
9. Error Handling
10. IP Core Architecture
11. Design Implementation
12. Debugging
13. Document Revision History
A. Transaction Layer Packet (TLP) Header Formats
B. Arria® 10 Avalon-ST with SR-IOV Interface for PCIe Solutions User Guide Archive

6.17. Virtual Function Registers

The SR-IOV Bridge implements the PCI and PCI Express Configuration Spaces for a maximum of 2048 Virtual Functions. The VF registers available are a subset of the PF registers. For example, the VFs do not implement the Link Capabilities 2 register. The definitions of VF registers are the same as PF registers. For additional details, refer to the PCI Express Base Specification 3.0.
Note: The following Virtual Function register map is applicable to all revisions of the Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe from the 18.1 release of Quartus® Prime onward.
Table 90.   Virtual Function Registers - Differences from PF

Address (hex)

Name

Description

0x000 Vendor ID and Device ID Register Vendor ID Register and Device ID Registers defined in PCI Express Base Specification 3.0 . These registers are hardwired to all 1s.
0x004 Command and Status Register PCI Command and Status Registers. Refer to Command and Status Register for VFs for descriptions of the implemented fields.
0x008 Revision ID and Class Code Register PCI Revision ID and Class Code Registers defined in PCI Express Base Specification 3.0 . The VF has the same settings and access as PF0.
0x00C BIST, Header Type, Latency Timer and Cache Line Size Registers Contains the following registers defined in the PCI Express Base Specification 3.0 : BIST Register, Header Type Register, Latency Timer, Cache Line Size Register. These registers are hardwired to all 0s for VFs.
0x010:

0x028

Reserved N/A
0x02C Subsystem Vendor ID and Subsystem ID Registers PCI Subsystem Vendor ID and Subsystem ID Registers. The VF has the same settings and access as PF0.
0x030 Reserved N/A
0x034 Capabilities Pointer This register points to the first Capability Structure in the PCI Configuration Space. For VFs, it points to the MSI-X capability.
0x038:

0x03C

Reserved N/A

MSI-X Capability Structure

0x07C

MSI-X Control Register

Contains the MSI-X Message Control Register, Capability ID for MSI-X, and the next capability pointer. The VF has the same fields and access as the parent PF.

0x080

MSI-X Table Offset

Points to the MSI-X Table in memory. Also specifies the BAR corresponding to the memory segment where the MSI-X Table resides. The VF has the same fields and access as the PF.

0x084

MSI-X PBA Offset

Points to the MSI-X Pending Bit Array in memory. Also, specifies the BAR corresponding to the memory segment where the PBA Array resides. The VF has the same fields and access as the parent PF.

PCI Express Capability Structure

0x040

PCI Express Capability List Register

Capability ID, PCI Express Capabilities Register, and the next capability pointer. Refer to cite="PCI Express Capability List Register for VFs" for descriptions of the implemented fields.

0x044

PCI Express Device Capabilities Register

PCI Express Device Capabilities Register. The VF Device Capabilities Register supports the same fields as the PF Device Capabilities Register.

0x048

PCI Express Device Control and Status Registers

The lower 16 bits implement the PCI Express Device Control Register. The upper 16 bits implement the Device Status Register. Refer to PCI Express Devices Control and Status Registers for VFs for descriptions of the implemented fields.

0x04C

Link Capabilities Register

A read to any VF with this address returns the Link Capabilities Register settings of the parent PF.

0x050

Link Control and Status Registers

This register is not implemented for VFs, and reads as all 0s.

0x054

Device Capabilities 2 Registers

A read to any VF with this address returns the Device Capabilities 2 Register settings of the parent PF.

0x058

Device Control 2 and Status 2 Registers

This register is not implemented for VFs. A read to this address returns all 0s.

0x05C

Link Capabilities 2 Register

This register is not implemented for VFs. A read to this address returns all 0s.

0x060 Link Control 2 and Status 2 Registers This register contains control and status bits for the PCIe link. For VFs, bit[16] stores the current de-emphasis level setting for the parent PF. All other bits are reserved.

Alternate RID (ARI) Capability Structure

0x100

ARI Enhanced Capability Header

PCI Express Extended Capability ID for ARI and Next Capability pointer. The Next Capability pointer points to NULL.

0x104

ARI Capability Register, ARI Control Register

This register is not implemented for VFs. A read to this address returns all 0s.

Transaction Processing Hints (TPH) Requester Capability Structure
0x300 TPH Requester Extended Capability Header PCI Express Extended Capability ID for TPH Requester Capability, and next capability pointer.
0x304 TPH Requester Capability Register This register contains the advertised parameters for the TPH Requester Capability.
0x308 TPH Requester Control Register This register contains enable and mode select bits for the TPH Requester Capability.
Address Translation Services (ATS) Capability Structure
0x3C0 ATS Extended Capability Header PCI Express Extended Capability ID for ATS Capability, and next capability pointer.
0x3C4 ATS Capability Register and ATS Control Register This location contains the 16-bit ATS Capability Register and the 16-bit ATS Control Register.
Table 91.  Command and Status Register for VFs - 0x004

Bits

Register Description

Default Value

Access

[1:0] Reserved. 0 RO
[2] Bus Master enable. When set, the VF can generate transactions as a bus master. 0 RW
[19:3] Reserved. 0 RO
[20] Indicates the presence of PCI Extended Capabilities. This bit is hardwired to 1. 1 RO
[23:21] Reserved. 0 RO
[24]
Master Data Parity Error: The device sets this bit when when the following occurs:
  • It has received a poisoned Completion directed at this VF
  • This VF has sent a poisoned memory write request on the link

This bit can only be set if the Parity Error Response Enable bit of the PCI Command Register of the parent PF is 1.

This bit is cleared by writing a 1. 		0 RW1C
[26:25] Reserved. 0 RO
[27]

Signaled Target Abort: The device sets this bit when this VF has sent a Completion with the Completer Abort (CA) status to the link.

This bit is cleared by writing a 1 		0 RW1C
[28]

Received Target Abort: The device sets this bit when it has received a Completion with the Completer Abort (CA) status targeting t this VF.

This bit is cleared by writing a 1 		0 RW1C
[29]

Received Master Abort: The device sets this bit when it has received a Completion with the Unsupported Request (UR) status targeting this VF.

This bit is cleared by writing a 1 		0 RW1C
[30]

Signaled System Error: The VF sets this bit when it has sent Fatal or Non-Fatal error message to the Root Complex. This bit can only be set if the SERR Enable bit of the PCI Command Register of the parent PF is enabled.

This bit is cleared by writing a 1. 		0 RW1C
[31]

Received Master Abort: The VF sets this bit when it has received a Completion with the Unsupported Request (UR) status.

This bit is cleared by writing a 1 		0 RW1C
Table 92.  PCI Express Capability List Register for VFs - 0x080

Bits

Register Description

Default Value

Access

[31:19] Hardwired to 0. 2 RO
[18:16] Version ID: Version of PCI Express Capability. 0 RW
[15:8] Next Capability Pointer: Points to NULL. 0 RO
[7:0] Capability ID assigned by PCI-SIG. 0x10 RO
Table 93.  PCI Express Device Control and Status Registers for VFs - 0x088

Bits

Register Description

Default Value

Access

Control Register

[14:0] Reserved. 0 RO
[15] Function-Level Reset. Writing a 1 to this bit generates a Function-Level Reset for this VF. Only functional when the PF Device Capabilities Register FLR Capable bit is set. This bit always reads as 0. 0 RW

Status Register

[16] Correctable Error Detected. 0 RW1C
[17] Non-Fatal Error Detected. 0 RW1C
[18] Fatal Error Detected. 0 RW1C
[19] Unsupported Request Detected. 0 RW1C
[20] Not implemented. 0 RO
[21] Transaction Pending. When set, indicates that a Non-Posted request issued by this VF is still pending. 0 RO
[31:22] Reserved. 0 RO
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