Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
Document Table of Contents

5.7. Function-Level Reset (FLR) Interface

The function-level reset (FLR) interface can reset the individual SR-IOV functions.

Table 28.  Function-Level Reset (FLR) Interface
Signal Width Direction Description

flr_active_pf

Number of PFs

Output

The SR-IOV Bridge asserts flr_active_pf when bit 15 of the PCIe Device Control Register is set. Bit 15 is the FLR field. This indicates to the user application that the Physical Function (PF) is undergoing a reset. Among the flr_active_pf bits, bit 0 is for PF0, bit 1 is for PF1, and so on.

Once asserted, the flr_active_pf signal remains high until the user application sets flr_completed_pf high for the associated function.

The user application must monitor these signals and perform actions necessary to clear any pending transactions associated with the function being reset. The user application must assert flr_completed_pf to indicate it has completed the FLR actions and is ready to re-enable the PF.

flr_rcvd_vf

1 Output

The SR-IOV Bridge asserts this output port for one cycle when a 1 is being written into the PCIe Device Control Register FLR field, bit[15], of a VF. flr_rcvd_pf_num and flr_rcvd_vf_num contain the PF number and the VF offset associated with the Function being reset.

The user application responds to a pulse on this output by clearing any pending transactions associated with the VF being reset. It then asserts flr_completed_vf to indicate that it has completed the FLR actions and is ready to re-enable the VF.

flr_rcvd_pf_num

1 - 3 Output When flr_rcvd_vf is asserted high, this output specifies the PF number associated with the VF undergoing FLR.

flr_rcvd_vf_num

1 - 11 Output

When flr_rcvd_vf is asserted high, this output specifies the VF number offset associated with the VF undergoing FLR.

flr_completed_pf

Number of PFs

Input

The assertion of this input for one or more cycles indicates that the application has completed resetting all the logic associated with the Physical Function. Among the flr_completed_pf bits, bit 0 is for PF0, bit 1 is for PF1, and so on. When the application sees flr_active_pf high, it must assert flr_completed_pf within 100 milliseconds to re-enable the Function.

flr_completed_vf

1

Input

The assertion of this input for one cycle indicates that the user application has completed resetting all the logic associated with the VF identified by the information placed on flr_completed_vf_num and flr_completed_pf_num.

The user application must assert flr_completed_vf within 100 milliseconds after receiving the FLR to re-enable the VF.

flr_completed_pf_num

1 - 3 Input When flr_completed_vf is asserted high, this input specifies the PF number associated with the VF that has completed its FLR.
flr_completed_vf_num 1 - 11 Input When flr_completed_vf is asserted high, this input specifies the VF number offset associated with the VF that has completed its FLR.
Figure 23. FLR Interface Timing Diagram for Physical Functions
Figure 24. FLR Interface Timing Diagram for Virtual Functions

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