Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide

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ID 683686
Date 1/11/2022
Public
Document Table of Contents

6.5. MSI-X Capability Structure

Figure 45. MSI-X Capability Registers - Byte Address Offsets and Layout
Table 51.  MSI-X Capability ID, Capability Pointer and Mask Register - 0x068

Bits

Register Description

Default Value

Access

[31]

MSI-X Enable. When set, enables MSI-X interrupt generation.

0

RW

[30]

MSI-X Function Mask. When set, masks all MSI-X interrupts from this function.

0

RW

[29:27]

Reserved.

0

RO

[26:16 ]

Size of the MSI-X Table. The value in this field is 1 less than the size of the table set up for this function. The maximum value is 0x7FF, or 4096 interrupt vectors.

Set in Platform Designer

RO

[15:8]

Next Capability Pointer. Points to Power Management Capability.

0x80

RO

[7:0]

Capability ID. PCI-SIG assigns this ID.

0x11

RO

Table 52.  MSI-X Table Offset BAR Indicator Register - 0x06C

Bits

Register Description

Default Value

Access

[2:0]

MSI-X Table BAR Indicator. Specifies the BAR number whose address range contains the MSI-X Table.

  • 3'b000: BAR0
  • 3'b001: BAR1
  • 3'b010: BAR2
  • 3'b011: BAR3
  • 3'b100: BAR4
  • 3'b101: BAR5

Set in Platform Designer

RO

[31:3]

Specifies the memory address offset for the MSI-X Table relative to the BAR base address value of the BAR number specified in MSI-X Table BAR Indicator,[2:0] above. The address is extended by appending 3 zeros to create quad-word alignment.

Set in Platform Designer

RO
Table 53.  MSI-X Pending Bit Array (PBA) Offset Register - 0x070

Bits

Register Description

Default Value

Access

[2:0]

MSI-X Pending Bit Array BAR Indicator. Specifies the BAR number whose address range contains the Pending Bit Array (PBA) table for this function. The following encodings are defined:

  • 3'b000: BAR0
  • 3'b001: BAR1
  • 3'b010: BAR2
  • 3'b011: BAR3
  • 3'b100: BAR4
  • 3'b101: BAR5

Set in Platform Designer

RO

[31:3]

Specifies the memory address offset for the PBA relative to the specified base address value of the BAR number specified in MSI-X Pending Bit Array BAR Indicator, at [2:0] above. The address is extended by appending 3 zeros to create quad-word alignment.

Set in Platform Designer

RO

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