Refer to Figure 8–16 on page 8–15 layout of headers and data for the 256‑bit Avalon‑ST packets with qword aligned and qword unaligned addresses.
Single Packet Per Cycle
In single packer per cycle mode, all received TLPs start at the lower 128-bit boundary on a 256-bit Avalon-ST interface. Turn on Enable Multiple Packets per Cycle on the System Settings tab of the parameter editor to change multiple packets per cycle.
Single packet per cycle mode requires simpler Application Layer packet decode logic on the TX and RX paths because packets always start in the lower 128-bits of the Avalon-ST interface. Although this mode simplifies the Application Layer logic, failure to use the full 256-bit Avalon-ST may slightly reduce the throughput of a design.
The following figure illustrates the layout of header and data for a three dword header on a 256‑bit bus with aligned and unaligned data.
The following figure illustrates the layout of header and data for a four dword header on a 256‑bit bus with aligned and unaligned data.
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