Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Public
Document Table of Contents

6.6.4. Correctable Internal Error Status Register

Table 59.  Correctable Internal Error Status Register The Correctable Internal Error Status register reports the status of the internally checked errors that are correctable. When these specific errors are enabled by the Correctable Internal Error Mask register, they are forwarded as Correctable Internal Errors as defined in the PCI Express Base Specification 3.0. This register is for debug only. Only use this register to observe behavior, not to drive logic custom logic.

Bits

Register Description

Reset Value

Access

[31:7]

Reserved.

0

RO

[6] Corrected Internal Error reported by the Application Layer. 0 RW1CS

[5]

When set, indicates a configuration error has been detected in CvP mode which is reported as correctable. This bit is set whenever a CVP_CONFIG_ERROR occurs while in CVP_MODE.

0

RW1CS

[4:2]

Reserved.

0

RO

[1]

When set, the retry buffer correctable ECC error status indicates an error.

0

RW1CS

[0]

When set, the RX buffer correctable ECC error status indicates an error.

0

RW1CS

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