Arria® 10 and Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide
ID
683647
Date
9/11/2024
Public
1. Datasheet
2. Quick Start Guide
3. Arria® 10 or Cyclone® 10 GX Parameter Settings
4. Physical Layout
5. Interfaces and Signal Descriptions
6. Registers
7. Reset and Clocks
8. Interrupts
9. Error Handling
10. PCI Express Protocol Stack
11. Transaction Layer Protocol (TLP) Details
12. Throughput Optimization
13. Design Implementation
14. Additional Features
15. Hard IP Reconfiguration
16. Testbench and Design Example
17. Debugging
A. Transaction Layer Packet (TLP) Header Formats
B. Lane Initialization and Reversal
C. Arria® 10 or Cyclone® 10 GX Avalon-ST Interface for PCIe Solutions User Guide Archive
D. Document Revision History
3.1. Parameters
3.2. Arria® 10 or Cyclone® 10 GX Avalon-ST Settings
3.3. Base Address Register (BAR) and Expansion ROM Settings
3.4. Base and Limit Registers for Root Ports
3.5. Device Identification Registers
3.6. PCI Express and PCI Capabilities Parameters
3.7. Vendor Specific Extended Capability (VSEC)
3.8. Configuration, Debug, and Extension Options
3.9. PHY Characteristics
3.10. Example Designs
5.1. Avalon‑ST RX Interface
5.2. Avalon-ST TX Interface
5.3. Clock Signals
5.4. Reset, Status, and Link Training Signals
5.5. ECRC Forwarding
5.6. Error Signals
5.7. Interrupts for Endpoints
5.8. Interrupts for Root Ports
5.9. Completion Side Band Signals
5.10. Parity Signals
5.11. LMI Signals
5.12. Transaction Layer Configuration Space Signals
5.13. Hard IP Reconfiguration Interface
5.14. Power Management Signals
5.15. Physical Layer Interface Signals
5.1.1. Avalon-ST RX Component Specific Signals
5.1.2. Data Alignment and Timing for the 64‑Bit Avalon® -ST RX Interface
5.1.3. Data Alignment and Timing for the 128‑Bit Avalon‑ST RX Interface
5.1.4. Data Alignment and Timing for 256‑Bit Avalon‑ST RX Interface
5.1.5. Tradeoffs to Consider when Enabling Multiple Packets per Cycle
5.2.1. Avalon-ST Packets to PCI Express TLPs
5.2.2. Data Alignment and Timing for the 64‑Bit Avalon-ST TX Interface
5.2.3. Data Alignment and Timing for the 128‑Bit Avalon‑ST TX Interface
5.2.4. Data Alignment and Timing for the 256‑Bit Avalon‑ST TX Interface
5.2.5. Root Port Mode Configuration Requests
16.4.1. ebfm_barwr Procedure
16.4.2. ebfm_barwr_imm Procedure
16.4.3. ebfm_barrd_wait Procedure
16.4.4. ebfm_barrd_nowt Procedure
16.4.5. ebfm_cfgwr_imm_wait Procedure
16.4.6. ebfm_cfgwr_imm_nowt Procedure
16.4.7. ebfm_cfgrd_wait Procedure
16.4.8. ebfm_cfgrd_nowt Procedure
16.4.9. BFM Configuration Procedures
16.4.10. BFM Shared Memory Access Procedures
16.4.11. BFM Log and Message Procedures
16.4.12. Verilog HDL Formatting Functions
14.1. Configuration over Protocol (CvP)
The Hard IP for PCI Express architecture has an option to configure the FPGA and initialize the PCI Express link. In prior devices, a single Program Object File (.pof) programmed the I/O ring and FPGA fabric before the PCIe link training and enumeration began. The .pof file is divided into two parts:
- The I/O bitstream contains the data to program the I/O ring, the Hard IP for PCI Express, and other elements that are considered part of the periphery image.
- The core bitstream contains the data to program the FPGA fabric.
When you select the CvP design flow, the I/O ring and PCI Express link are programmed first, allowing the PCI Express link to reach the L0 state and begin operation independently, before the rest of the core is programmed. After the PCI Express link is established, it can be used to program the rest of the device. The following figure shows the blocks that implement CvP.
Figure 103. CvP in Arria® 10 or Cyclone® 10 GX Devices
CvP has the following advantages:
- Provides a simpler software model for configuration. A smart host can use the PCIe protocol and the application topology to initialize and update the FPGA fabric.
- Improves security for the proprietary core bitstream.
- Reduces system costs by reducing the size of the flash device to store the .pof.
- May reduce system size because a single CvP link can be used to configure multiple FPGAs.
Note: The Cyclone® 10 GX CvP Initialization over PCI Express User Guide is now available.