Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Public
Document Table of Contents

5.5. Interrupts for Endpoints

Refer to Interrupts for detailed information about all interrupt mechanisms.

Table 30.  Interrupt Signals for Endpoints

Signal

Direction

Description

app_msi_req

Input

Application Layer MSI request. Assertion causes an MSI posted write TLP to be generated based on the MSI configuration register values and the app_msi_tc and app_msi_num input ports.

app_msi_ack

Output

Application Layer MSI acknowledge. This signal acknowledges the Application Layer's request for an MSI interrupt.

app_msi_tc[2:0]

Input

Application Layer MSI traffic class. This signal indicates the traffic class used to send the MSI (unlike INTX interrupts, any traffic class can be used to send MSIs).

app_msi_num[4:0]

Input

MSI number of the Application Layer. This signal provides the low order message data bits to be sent in the message data field of MSI messages requested by app_msi_req. Only bits that are enabled by the MSI Message Control register apply.

app_int_sts

Input

Controls legacy interrupts. Assertion of app_int_sts causes an Assert_INTA message TLP to be generated and sent upstream. Deassertion of app_int_sts causes a Deassert_INTA message TLP to be generated and sent upstream.

app_int_ack

Output

This signal is the acknowledge for app_int_sts. It is asserted for at least one cycle either when either of the following events occur:

  • The Assert_INTA message TLP has been transmitted in response to the assertion of the app_int_sts.
  • The Deassert_INTA message TLP has been transmitted in response to the deassertion of the app_int_sts signal.

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