Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Public
Document Table of Contents

A.2. TLP Packet Formats with Data Payload

Figure 82. Memory Write Request, 32-Bit Addressing
Figure 83. Memory Write Request, 64-Bit Addressing
Figure 84. Configuration Write Request Root Port (Type 1)
Figure 85. I/O Write Request
Figure 86. Completion with Data
Figure 87. Completion Locked with Data
Figure 88. Message with Data

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