Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Public
Document Table of Contents

10.1.1. INTX Messages

Table 67.  INTX Messages

Message

Root Port

Endpoint

Generated by

Comments

App Layer

Core

Core (with App Layer input)

Assert_INTA

Receive

Transmit

No

Yes

No

For Root Port, legacy interrupts are translated into message interrupt TLPs which triggers the int_status[3:0] signals to the Application Layer.

  • int_status[0]: Interrupt signal A
  • int_status[1]: Interrupt signal B
  • int_status[2]: Interrupt signal C
  • int_status[3]: Interrupt signal D

Assert_INTB

Receive

Transmit

No

No

No

Assert_INTC

Receive

Transmit

No

No

No

Assert_INTD

Receive

Transmit

No

No

No

Deassert_INTA

Receive

Transmit

No

Yes

No

Deassert_INTB

Receive

Transmit

No

No

No

Deassert_INTC

Receive

Transmit

No

No

No

Deassert_INTD

Receive

Transmit

No

No

No

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