Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Document Table of Contents

Clock Summary



Clock Domain


62.5, 125 or 250 MHz

Avalon‑ST interface between the Transaction and Application Layers.


pld_clk has a maximum frequency of 250 MHz and a minimum frequency that can be equal or more than the coreclkout_hip frequency, depending on the link width, link rate, and Avalon® interface width as indicated in the table for the Application Layer clock frequency above.

Application and Transaction Layers.


100 MHz

SERDES (transceiver). Dedicated free running input clock to the SERDES block.


Avalon‑MM interface for Hard IP dynamic reconfiguration interface which you can use to change the value of read‑only configuration registers at run‑time. This interface is optional. It is not required for Intel® Arria® 10 or Intel® Cyclone® 10 GX devices.