Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Public
Document Table of Contents

8.4. Error Reporting and Data Poisoning

How the Endpoint handles a particular error depends on the configuration registers of the device.

Refer to the PCI Express Base Specification 3.0 for a description of the device signaling and logging for an Endpoint.

The Hard IP block implements data poisoning, a mechanism for indicating that the data associated with a transaction is corrupted. Poisoned TLPs have the error/poisoned bit of the header set to 1 and observe the following rules:

  • Received poisoned TLPs are sent to the Application Layer and status bits are automatically updated in the Configuration Space.
  • Received poisoned Configuration Write TLPs are not written in the Configuration Space.
  • The Configuration Space never generates a poisoned TLP; the error/poisoned bit of the header is always set to 0.

Poisoned TLPs can also set the parity error bits in the PCI Configuration Space Status register.

Table 65.  Parity Error Conditions

Status Bit

Conditions

Detected parity error (status register bit 15)

Set when any received TLP is poisoned.

Master data parity error (status register bit 8)

This bit is set when the command register parity enable bit is set and one of the following conditions is true:

  • The poisoned bit is set during the transmission of a Write Request TLP.
  • The poisoned bit is set on a received completion TLP.

Poisoned packets received by the Hard IP block are passed to the Application Layer. Poisoned transmit TLPs are similarly sent to the link.

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