Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Document Table of Contents

A.1. TLP Packet Formats without Data Payload

The following figures show the header format for TLPs without a data payload.

For more information about the alignment of 3- and 4-dword headers refer to the related links below for Data Alignment and Timing for the Avalon-ST TX and RX Interfaces.

Figure 73. Memory Read Request, 32-Bit Addressing
Figure 74. Memory Read Request, Locked 32-Bit Addressing
Figure 75. Memory Read Request, 64-Bit Addressing
Figure 76. Memory Read Request, Locked 64-Bit Addressing
Figure 77. Configuration Read Request Root Port (Type 1)
Figure 78. I/O Read Request
Figure 79. Message without Data

Figure 80. Completion without Data
Figure 81. Completion Locked without Data