Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Public
Document Table of Contents

6.5. Intel-Defined VSEC Registers

Figure 47. VSEC RegistersThis extended capability structure supports Configuration via Protocol (CvP) programming and detailed internal error reporting.
Table 47.   Intel‑Defined VSEC Capability Register, 0x200The Intel‑Defined Vendor Specific Extended Capability. This extended capability structure supports Configuration via Protocol (CvP) programming and detailed internal error reporting.

Bits

Register Description

Value

Access

[15:0]

PCI Express Extended Capability ID. Intel-defined value for VSEC Capability ID.

0x000B

RO

[19:16]

Version. Intel-defined value for VSEC version.

0x1

RO

[31:20]

Next Capability Offset. Starting address of the next Capability Structure implemented, if any.

Variable

RO

Table 48.   Intel‑Defined Vendor Specific Header You can specify these values when you instantiate the Hard IP. These registers are read‑only at run‑time.

Bits

Register Description

Value

Access

[15:0]

VSEC ID. A user configurable VSEC ID.

User entered

RO

[19:16]

VSEC Revision. A user configurable VSEC revision.

Variable

RO

[31:20]

VSEC Length. Total length of this structure in bytes.

0x044

RO

Table 49.   Intel Marker Register

Bits

Register Description

Value

Access

[31:0]

Intel Marker. This read only register is an additional marker. If you use the standard Intel Programmer software to configure the device with CvP, this marker provides a value that the programming software reads to ensure that it is operating with the correct VSEC.

A Device Value

RO

Table 50.  JTAG Silicon ID Register

Bits

Register Description

Value

Access

[127:96]

JTAG Silicon ID DW3

Application Specific

RO

[95:64]

JTAG Silicon ID DW2

Application Specific

RO

[63:32]

JTAG Silicon ID DW1

Application Specific

RO

[31:0]

JTAG Silicon ID DW0. This is the JTAG Silicon ID that CvP programming software reads to determine that the correct SRAM object file (.sof) is being used.

Application Specific

RO

Table 51.  User Device or Board Type ID Register

Bits

Register Description

Value

Access

[15:0]

Configurable device or board type ID to specify to CvP the correct .sof.

Variable

RO

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