Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Public
Document Table of Contents
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16.1. Simulation Fails To Progress Beyond Polling.Active State

If your PIPE simulation cycles between the Detect.Quiet, Detect.Active, and Polling.Active LTSSM states, the PIPE interface width may be incorrect.

Make the changes shown in the following table for the 32-bit PIPE interface.

Table 81.  Changes for 32-Bit PIPE Interface
8-Bit PIPE Interface 32-Bit PIPE Interface
output wire [7:0] pcie_a10_hip_0_hip_pipe_txdata0 output wire [31:0] pcie_a10_hip_0_hip_pipe_txdata0
input wire [7:0] pcie_a10_hip_0_hip_pipe_rxdata0 input wire [31:0] pcie_a10_hip_0_hip_pipe_rxdata0
output wire pcie_a10_simulation_inst_pcie_a10_hip_0_hip_pipe_txdatak0 output wire [3:0] pcie_a10_simulation_inst_pcie_a10_hip_0_hip_pipe_txdatak0
input wire pcie_a10_simulation_inst_pcie_a10_hip_0_hip_pipe_rxdatak0 input wire [3:0] pcie_a10_simulation_inst_pcie_a10_hip_0_hip_pipe_rxdatak0