Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Public
Document Table of Contents

5.1. Clock Signals

Table 26.  Clock Signals

Signal

Direction

Description

refclk

Input

Reference clock for the IP core. It must have the frequency specified under the System Settings heading in the parameter editor. This is a dedicated free running input clock to the dedicated REFCLK pin.

pld_clk

Input

Clocks the Application Layer. You can drive this clock with coreclkout_hip. If you drive pld_clk with another clock source, it must be equal to or faster than coreclkout_hip, but cannot be faster than 250 MHz. Choose a clock source with a 0 ppm accuracy if pld_clk is operating at the same frequency as coreclkout_hip.

coreclkout_hip

Output

This is a fixed frequency clock used by the Data Link and Transaction Layers.

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