14. Hard IP Reconfiguration
The Intel® Arria® 10 or Intel® Cyclone® 10 GX Hard IP for PCI Express reconfiguration block allows you to dynamically change the value of configuration registers that are read-only. You access this block using its Avalon-MM slave interface. You must enable this optional functionality by turning on Enable Hard IP Reconfiguration in the parameter editor. For a complete description of the signals in this interface, refer to Hard IP Reconfiguration Interface.
The Hard IP reconfiguration block provides access to read-only configuration registers, including Configuration Space, Link Configuration, MSI and MSI-X capabilities, Power Management, and Advanced Error Reporting (AER). This interface does not support simulation.
The procedure to dynamically reprogram these registers includes the following three steps:
- Bring down the PCI Express link by asserting the hip_reconfig_rst_n reset signal, if the link is already up. (Reconfiguration can occur before the link has been established.)
- Reprogram configuration registers using the Avalon-MM slave Hard IP reconfiguration interface.
- Release the npor reset signal.
Contact your Intel representative for descriptions of the read-only, reconfigurable registers.
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