Arria® 10 and Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

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ID 683647
Date 9/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Quick Start Guide 3. Arria® 10 or Cyclone® 10 GX Parameter Settings 4. Physical Layout 5. Interfaces and Signal Descriptions 6. Registers 7. Reset and Clocks 8. Interrupts 9. Error Handling 10. PCI Express Protocol Stack 11. Transaction Layer Protocol (TLP) Details 12. Throughput Optimization 13. Design Implementation 14. Additional Features 15. Hard IP Reconfiguration 16. Testbench and Design Example 17. Debugging A. Transaction Layer Packet (TLP) Header Formats B. Lane Initialization and Reversal C. Arria® 10 or Cyclone® 10 GX Avalon-ST Interface for PCIe Solutions User Guide Archive D. Document Revision History
1. Datasheet x
1.1. Arria® 10 or Cyclone® 10 GX Avalon-ST Interface for PCI Express* Datasheet 1.2. Release Information 1.3. Device Family Support 1.4. Configurations 1.5. Debug Features 1.6. IP Core Verification 1.7. Resource Utilization 1.8. Recommended Speed Grades 1.9. Creating a Design for PCI Express
1.1. Arria® 10 or Cyclone® 10 GX Avalon-ST Interface for PCI Express* Datasheet x
1.1.1. Arria® 10 or Cyclone® 10 GX Features
1.6. IP Core Verification x
1.6.1. Compatibility Testing Environment
2. Quick Start Guide x
2.1. Directory Structure 2.2. Design Components 2.3. Generating the Design 2.4. Simulating the Design 2.5. Compiling and Testing the Design in Hardware
3. Arria® 10 or Cyclone® 10 GX Parameter Settings x
3.1. Parameters 3.2. Arria® 10 or Cyclone® 10 GX Avalon-ST Settings 3.3. Base Address Register (BAR) and Expansion ROM Settings 3.4. Base and Limit Registers for Root Ports 3.5. Device Identification Registers 3.6. PCI Express and PCI Capabilities Parameters 3.7. Vendor Specific Extended Capability (VSEC) 3.8. Configuration, Debug, and Extension Options 3.9. PHY Characteristics 3.10. Example Designs
3.6. PCI Express and PCI Capabilities Parameters x
3.6.1. PCI Express and PCI Capabilities 3.6.2. Error Reporting 3.6.3. Link Capabilities 3.6.4. MSI and MSI-X Capabilities 3.6.5. Slot Capabilities 3.6.6. Power Management
4. Physical Layout x
4.1. Hard IP Block Placement In Cyclone® 10 GX Devices 4.2. Hard IP Block Placement In Arria® 10 Devices 4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates 4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate 4.5. PCI Express Gen3 Bank Usage Restrictions
5. Interfaces and Signal Descriptions x
5.1. Clock Signals 5.2. Reset, Status, and Link Training Signals 5.3. ECRC Forwarding 5.4. Error Signals 5.5. Interrupts for Endpoints 5.6. Interrupts for Root Ports 5.7. Completion Side Band Signals 5.8. Parity Signals 5.9. LMI Signals 5.10. Transaction Layer Configuration Space Signals 5.11. Hard IP Reconfiguration Interface 5.12. Power Management Signals 5.13. Physical Layer Interface Signals
5.10. Transaction Layer Configuration Space Signals x
5.10.1. Configuration Space Register Access Timing 5.10.2. Configuration Space Register Access
5.13. Physical Layer Interface Signals x
5.13.1. Serial Data Signals 5.13.2. PIPE Interface Signals 5.13.3. Test Signals 5.13.4. Arria® 10 Development Kit Conduit Interface
6. Registers x
6.1. Correspondence between Configuration Space Registers and the PCIe Specification 6.2. Type 0 Configuration Space Registers 6.3. Type 1 Configuration Space Registers 6.4. PCI Express Capability Structures 6.5. Intel-Defined VSEC Registers 6.6. Advanced Error Reporting Capability
6.5. Intel-Defined VSEC Registers x
6.5.1. CvP Registers
6.6. Advanced Error Reporting Capability x
6.6.1. Uncorrectable Internal Error Mask Register 6.6.2. Uncorrectable Internal Error Status Register 6.6.3. Correctable Internal Error Mask Register 6.6.4. Correctable Internal Error Status Register
7. Reset and Clocks x
7.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer 7.2. Clocks
7.2. Clocks x
7.2.1. Clock Domains 7.2.2. Clock Summary
7.2.1. Clock Domains x
7.2.1.1. coreclkout_hip 7.2.1.2. pld_clk
8. Interrupts x
8.1. Interrupts for Endpoints 8.2. Interrupts for Root Ports
8.1. Interrupts for Endpoints x
8.1.1. MSI and Legacy Interrupts 8.1.2. MSI-X 8.1.3. Implementing MSI-X Interrupts 8.1.4. Legacy Interrupts
9. Error Handling x
9.1. Physical Layer Errors 9.2. Data Link Layer Errors 9.3. Transaction Layer Errors 9.4. Error Reporting and Data Poisoning 9.5. Uncorrectable and Correctable Error Status Bits
10. PCI Express Protocol Stack x
10.1. Top-Level Interfaces 10.2. Transaction Layer 10.3. Data Link Layer 10.4. Physical Layer
10.1. Top-Level Interfaces x
10.1.1. Avalon-ST Interface 10.1.2. Clocks and Reset 10.1.3. Local Management Interface (LMI Interface) 10.1.4. Hard IP Reconfiguration 10.1.5. Interrupts 10.1.6. PIPE
10.2. Transaction Layer x
10.2.1. Configuration Space
11. Transaction Layer Protocol (TLP) Details x
11.1. Supported Message Types 11.2. Transaction Layer Routing Rules 11.3. Receive Buffer Reordering
11.1. Supported Message Types x
11.1.1. INTX Messages 11.1.2. Power Management Messages 11.1.3. Error Signaling Messages 11.1.4. Locked Transaction Message 11.1.5. Slot Power Limit Message 11.1.6. Vendor-Defined Messages 11.1.7. Hot Plug Messages
11.3. Receive Buffer Reordering x
11.3.1. Using Relaxed Ordering
12. Throughput Optimization x
12.1. Throughput of Posted Writes 12.2. Throughput of Non-Posted Reads
13. Design Implementation x
13.1. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 13.2. Recommended Reset Sequence to Avoid Link Training Issues 13.3. SDC Timing Constraints
14. Additional Features x
14.1. Configuration over Protocol (CvP) 14.2. Autonomous Mode 14.3. ECRC
14.2. Autonomous Mode x
14.2.1. Enabling Autonomous Mode 14.2.2. Enabling CvP Initialization
14.3. ECRC x
14.3.1. ECRC on the RX Path 14.3.2. ECRC on the TX Path
16. Testbench and Design Example x
16.1. Endpoint Testbench 16.2. Test Driver Module 16.3. Root Port BFM Overview 16.4. BFM Procedures and Functions
16.1. Endpoint Testbench x
16.1.1. Endpoint Testbench for SR-IOV
16.3. Root Port BFM Overview x
16.3.1. BFM Memory Map 16.3.2. Configuration Space Bus and Device Numbering 16.3.3. Configuration of Root Port and Endpoint 16.3.4. Issuing Read and Write Transactions to the Application Layer
16.4. BFM Procedures and Functions x
16.4.1. ebfm_barwr Procedure 16.4.2. ebfm_barwr_imm Procedure 16.4.3. ebfm_barrd_wait Procedure 16.4.4. ebfm_barrd_nowt Procedure 16.4.5. ebfm_cfgwr_imm_wait Procedure 16.4.6. ebfm_cfgwr_imm_nowt Procedure 16.4.7. ebfm_cfgrd_wait Procedure 16.4.8. ebfm_cfgrd_nowt Procedure 16.4.9. BFM Configuration Procedures 16.4.10. BFM Shared Memory Access Procedures 16.4.11. BFM Log and Message Procedures 16.4.12. Verilog HDL Formatting Functions
16.4.9. BFM Configuration Procedures x
16.4.9.1. ebfm_cfg_rp_ep Procedure 16.4.9.2. ebfm_cfg_decode_bar Procedure
16.4.10. BFM Shared Memory Access Procedures x
16.4.10.1. Shared Memory Constants 16.4.10.2. shmem_write Task 16.4.10.3. shmem_read Function 16.4.10.4. shmem_display Verilog HDL Function 16.4.10.5. shmem_fill Procedure 16.4.10.6. shmem_chk_ok Function
16.4.11. BFM Log and Message Procedures x
16.4.11.1. ebfm_display Verilog HDL Function 16.4.11.2. ebfm_log_stop_sim Verilog HDL Function 16.4.11.3. ebfm_log_set_suppressed_msg_mask Task 16.4.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 16.4.11.5. ebfm_log_open Verilog HDL Function 16.4.11.6. ebfm_log_close Verilog HDL Function
16.4.12. Verilog HDL Formatting Functions x
16.4.12.1. himage1 16.4.12.2. himage2 16.4.12.3. himage4 16.4.12.4. himage8 16.4.12.5. himage16 16.4.12.6. dimage1 16.4.12.7. dimage2 16.4.12.8. dimage3 16.4.12.9. dimage4 16.4.12.10. dimage5 16.4.12.11. dimage6 16.4.12.12. dimage7
17. Debugging x
17.1. Simulation Fails To Progress Beyond Polling.Active State 17.2. Hardware Bring-Up Issues 17.3. Link Training 17.4. Creating a Signal Tap Debug File to Match Your Design Hierarchy 17.5. Use Third-Party PCIe Analyzer 17.6. BIOS Enumeration Issues
17.3. Link Training x
17.3.1. Link Hangs in L0 State
A. Transaction Layer Packet (TLP) Header Formats x
A.1. TLP Packet Formats without Data Payload A.2. TLP Packet Formats with Data Payload
D. Document Revision History x
D.1. Document Revision History of the Arria® 10 or Cyclone® 10 GX Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide
1. Datasheet
2. Quick Start Guide
3. Arria® 10 or Cyclone® 10 GX Parameter Settings
4. Physical Layout
5. Interfaces and Signal Descriptions
6. Registers
7. Reset and Clocks
8. Interrupts
9. Error Handling
10. PCI Express Protocol Stack
11. Transaction Layer Protocol (TLP) Details
12. Throughput Optimization
13. Design Implementation
14. Additional Features
15. Hard IP Reconfiguration
16. Testbench and Design Example
17. Debugging
A. Transaction Layer Packet (TLP) Header Formats
B. Lane Initialization and Reversal
C. Arria® 10 or Cyclone® 10 GX Avalon-ST Interface for PCIe Solutions User Guide Archive
D. Document Revision History

6.1. Correspondence between Configuration Space Registers and the PCIe Specification

Table 46.  Address Map of Hard IP Configuration Space RegistersFor the Type 0 and Type 1 Configuration Space Headers, the first line of each entry lists Type 0 values and the second line lists Type 1 values when the values differ.

Byte Address

Hard IP Configuration Space Register

Corresponding Section in PCIe Specification

0x000:0x03C

PCI Header Type 0 Configuration Registers

Type 0 Configuration Space Header

0x000:0x03C

PCI Header Type 1 Configuration Registers

Type 1 Configuration Space Header

0x040:0x04C

Reserved

N/A

0x050:0x05C

MSI Capability Structure

MSI Capability Structure

0x068:0x070

MSI-X Capability Structure

MSI-X Capability Structure

0x070:0x074

Reserved

N/A

0x078:0x07C

Power Management Capability Structure

PCI Power Management Capability Structure

0x080:0x0BC

PCI Express Capability Structure

PCI Express Capability Structure

0x0C0:0x0FC

Reserved

N/A

0x100:0x16C

Virtual Channel Capability Structure

Virtual Channel Capability

0x170:0x17C

Reserved

N/A

0x180:0x1FC

Virtual channel arbitration table

VC Arbitration Table

0x200:0x23C

Port VC0 arbitration table

Port Arbitration Table

0x240:0x27C

Port VC1 arbitration table

Port Arbitration Table

0x280:0x2BC

Port VC2 arbitration table

Port Arbitration Table

0x2C0:0x2FC

Port VC3 arbitration table

Port Arbitration Table

0x300:0x33C

Port VC4 arbitration table

Port Arbitration Table

0x340:0x37C

Port VC5 arbitration table

Port Arbitration Table

0x380:0x3BC

Port VC6 arbitration table

Port Arbitration Table

0x3C0:0x3FC

Port VC7 arbitration table

Port Arbitration Table

0x400:0x7FC

Reserved

PCIe spec corresponding section name

0x800:0x834

Advanced Error Reporting AER (optional)

Advanced Error Reporting Capability

0x838:0xFFF

Reserved

N/A

Overview of Configuration Space Register Fields

0x000

Device ID, Vendor ID

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x004

Status, Command

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x008

Class Code, Revision ID

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x00C

BIST, Header Type, Primary Latency Timer, Cache Line Size

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x010

Base Address 0

Base Address Registers

0x014

Base Address 1

Base Address Registers

0x018

Base Address 2

Secondary Latency Timer, Subordinate Bus Number, Secondary Bus Number, Primary Bus Number

Base Address Registers

Secondary Latency Timer, Type 1 Configuration Space Header, Primary Bus Number

0x01C

Base Address 3

Secondary Status, I/O Limit, I/O Base

Base Address Registers

Secondary Status Register ,Type 1 Configuration Space Header

0x020

Base Address 4

Memory Limit, Memory Base

Base Address Registers

Type 1 Configuration Space Header

0x024

Base Address 5

Prefetchable Memory Limit, Prefetchable Memory Base

Base Address Registers

Prefetchable Memory Limit, Prefetchable Memory Base

0x028

Reserved

Prefetchable Base Upper 32 Bits

N/A

Type 1 Configuration Space Header

0x02C

Subsystem ID, Subsystem Vendor ID

Prefetchable Limit Upper 32 Bits

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x030

Expansion ROM base address

I/O Limit Upper 16 Bits, I/O Base Upper 16 Bits

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x034

Reserved, Capabilities PTR

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x038

Reserved

Expansion ROM Base Address

N/A

Type 1 Configuration Space Header

0x03C

Interrupt Pin, Interrupt Line

Bridge Control, Interrupt Pin, Interrupt Line

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x050

MSI-Message Control Next Cap Ptr Capability ID

MSI and MSI-X Capability Structures

0x054

Message Address

MSI and MSI-X Capability Structures

0x058

Message Upper Address

MSI and MSI-X Capability Structures

0x05C

Reserved Message Data

MSI and MSI-X Capability Structures

0x068

MSI-X Message Control Next Cap Ptr Capability ID

MSI and MSI-X Capability Structures

0x06C

MSI-X Table Offset BIR

MSI and MSI-X Capability Structures

0x070

Pending Bit Array (PBA) Offset BIR

MSI and MSI-X Capability Structures

0x078

Capabilities Register Next Cap PTR Cap ID

PCI Power Management Capability Structure

0x07C

Data PM Control/Status Bridge Extensions Power Management Status & Control

PCI Power Management Capability Structure

0x080

PCI Express Capabilities Register Next Cap Ptr PCI Express Cap ID

PCI Express Capability Structure

0x084

Device Capabilities Register

PCI Express Capability Structure

0x088

Device Status Register Device Control Register

PCI Express Capability Structure

0x08C

Link Capabilities Register

PCI Express Capability Structure

0x090

Link Status Register Link Control Register

PCI Express Capability Structure

0x094

Slot Capabilities Register

PCI Express Capability Structure

0x098

Slot Status Register Slot Control Register

PCI Express Capability Structure

0x09C

Root Capabilities Register Root Control Register

PCI Express Capability Structure

0x0A0

Root Status Register

PCI Express Capability Structure

0x0A4

Device Capabilities 2 Register

PCI Express Capability Structure

0x0A8

Device Status 2 Register Device Control 2 Register

PCI Express Capability Structure

0x0AC

Link Capabilities 2 Register

PCI Express Capability Structure

0x0B0

Link Status 2 Register Link Control 2 Register

PCI Express Capability Structure

0x0B4:0x0BC

Reserved

PCI Express Capability Structure

0x800

Advanced Error Reporting Enhanced Capability Header

Advanced Error Reporting Enhanced Capability Header

0x804

Uncorrectable Error Status Register

Uncorrectable Error Status Register

0x808

Uncorrectable Error Mask Register

Uncorrectable Error Mask Register

0x80C

Uncorrectable Error Severity Register

Uncorrectable Error Severity Register

0x810

Correctable Error Status Register

Correctable Error Status Register

0x814

Correctable Error Mask Register

Correctable Error Mask Register

0x818

Advanced Error Capabilities and Control Register

Advanced Error Capabilities and Control Register

0x81C

Header Log Register

Header Log Register

0x82C

Root Error Command

Root Error Command Register

0x830

Root Error Status

Root Error Status Register

0x834

Error Source Identification Register Correctable Error Source ID Register

Error Source Identification Register

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