Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Public
Document Table of Contents

7.2. Interrupts for Root Ports

In Root Port mode, the Intel® Arria® 10 or Intel® Cyclone® 10 GX Hard IP for PCI Express receives interrupts through two different mechanisms:

  • MSI—Root Ports receive MSI interrupts through the Avalon-ST RX Memory Write TLP. This is a memory mapped mechanism.
  • Legacy—Legacy interrupts are translated into Message Interrupt TLPs and sent to the Application Layer using the int_status pins.

Normally, the Root Port services rather than sends interrupts; however, in two circumstances the Root Port can send an interrupt to itself to record error conditions:

  • When the AER option is enabled, the aer_msi_num[4:0] signal indicates which MSI is being sent to the root complex when an error is logged in the AER Capability structure. This mechanism is an alternative to using the serr_out signal. The aer_msi_n um[4:0] is only used for Root Ports and you must set it to a constant value. It cannot toggle during operation.
  • If the Root Port detects a Power Management Event, the pex_msi_num[4:0] signal is used by Power Management or Hot Plug to determine the offset between the base message interrupt number and the message interrupt number to send through MSI. The user must set pex_msi_num[4:0]to a fixed value.

The Root Error Status register reports the status of error messages. The Root Error Status register is part of the PCI Express AER Extended Capability structure. It is located at offset 0x830 of the Configuration Space registers.

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