The following figure shows the location of headers and data for the 256‑bit Avalon‑ST packets. This layout of data applies to both the TX and RX buses.
The following figure illustrates two single-cycle 256‑bit packets. The first packet has two empty dwords, rx_st_data[191:0] is valid. The second packet has four empty dwords; rx_st_data[127:0] is valid.
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