Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Document Table of Contents

Location of Headers and Data for Avalon-ST 256-Bit Interface

The following figure shows the location of headers and data for the 256‑bit Avalon‑ST packets. This layout of data applies to both the TX and RX buses.

256-Bit Avalon-ST RX Packets Use of rx_st_empty and Single-Cycle Packets

The following figure illustrates two single-cycle 256‑bit packets. The first packet has two empty dwords, rx_st_data[191:0] is valid. The second packet has four empty dwords; rx_st_data[127:0] is valid.

Did you find the information on this page useful?

Characters remaining:

Feedback Message