Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Document Table of Contents

4.2. Hard IP Block Placement In Intel® Arria® 10 Devices

Intel® Arria® 10 devices include 1–4 hard IP blocks for PCI Express. The bottom left hard IP block includes the CvP functionality for flip chip packages. For other package types, the CvP functionality is in the bottom right block.
Note: Intel® Arria® 10 devices do not support configurations that configure a bottom (left or right) hard IP block with a Gen3 x4 or Gen3 x8 IP core and also configure the top hard IP block on the same side with a Gen3 x1 or Gen3 x2 IP core variation.
Figure 18.  Intel® Arria® 10 Devices with 72 Transceiver Channels and Four PCIe Hard IP Blocks
Figure 19.  Intel® Arria® 10 Devices with 96 Transceiver Channels and Four PCIe Hard IP Blocks
Figure 20.  Intel® Arria® 10 GT Devices with 48 Transceiver Channels and Two PCIe Hard IP Blocks

Refer to the Intel® Arria® 10 Transceiver Layout in the Intel® Arria® 10 for comprehensive figures for Intel® Arria® 10 GT, GX, and SX devices.

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