Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Document Table of Contents

9.2.1. Configuration Space

The Configuration Space implements the following configuration registers and associated functions:

  • Header Type 0 Configuration Space for Endpoints
  • Header Type 1 Configuration Space for Root Ports
  • PCI Power Management Capability Structure
  • Virtual Channel Capability Structure
  • Message Signaled Interrupt (MSI) Capability Structure
  • Message Signaled Interrupt–X (MSI–X) Capability Structure
  • PCI Express Capability Structure
  • Advanced Error Reporting (AER) Capability Structure
  • Vendor Specific Extended Capability (VSEC)

The Configuration Space also generates all messages (PME#, INT, error, slot power limit), MSI requests, and completion packets from configuration requests that flow in the direction of the root complex, except slot power limit messages, which are generated by a downstream port. All such transactions are dependent upon the content of the PCI Express Configuration Space as described in the PCI Express Base Specification.

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