Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Public
Document Table of Contents

3.4. Base and Limit Registers for Root Ports

Table 14.   Base and Limit Registers The following table describes the Base and Limit registers which are available in the Type 1 Configuration Space for Root Ports. These registers are used for TLP routing and specify the address ranges assigned to components that are downstream of the Root Port or bridge.

Parameter

Value

Description

Input/Output

Disabled

16-bit I/O addressing

32-bit I/O addressing

Specifies the address widths for the IO base and IO limit registers.

Prefetchable memory

Disabled

16-bit memory addressing

32-bit memory addressing

Specifies the address widths for the Prefetchable Memory Base register and Prefetchable Memory Limit register.

Note: The Avalon‑MM Hard IP for PCI Express Root Port does not filter addresses.

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