Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Public
Document Table of Contents

3.3. Base Address Register (BAR) and Expansion ROM Settings

The type and size of BARs available depend on port type.

Table 13.  BAR Registers

Parameter

Value

Description

Type

Disabled

64-bit prefetchable memory

32-bit non-prefetchable memory

32-bit prefetchable memory

I/O address space

If you select 64-bit prefetchable memory, 2 contiguous BARs are combined to form a 64-bit prefetchable BAR; you must set the higher numbered BAR to Disabled. A non-prefetchable 64‑bit BAR is not supported because in a typical system, the Root Port Type 1 Configuration Space sets the maximum non‑prefetchable memory window to 32 bits. The BARs can also be configured as separate 32‑bit memories.

Defining memory as prefetchable allows contiguous data to be fetched ahead. Prefetching memory is advantageous when the requestor may require more data from the same region than was originally requested. If you specify that a memory is prefetchable, it must have the following 2 attributes:

  • Reads do not have side effects such as changing the value of the data read
  • Write merging is allowed

Size

16 Bytes–8 EB

Supports the following memory sizes:

  • 128 bytes–2 GB or 8 EB: Endpoint and Root Port variants
  • 16 bytes–4 KB: Legacy Endpoint variants I/O space BARs

Expansion ROM

Disabled–16 MB

Specifies the size of the optional ROM.

The expansion ROM is only available for the Avalon‑ST interface.

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